Abstract: An adapter assembly and a projection device are provided. The projection device includes a device body, an illumination system, a light valve, the adapter assembly, and a projection lens. The light valve is disposed in the device body to convert the illuminating beam provided by the illumination system into an image beam. The projection lens includes a plurality of protruding claws that surround a circumferential surface of a main body and protrude along the radial direction. The adapter assembly includes a first ring member, a rotating plate, and a second ring member sequentially disposed along the axial direction of the adapter assembly. When the projection lens is assembled to the adapter assembly, the rotating plate rotates to limit the protruding claws within a limiting assembly space formed by the first ring member and the second ring member to lock the projection lens to the device body.

Abstract: The present invention provides a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving a first data from a host device; storing the first data in the first buffer memory; transmitting the first data to the first memory portion of the flash memory module from the first buffer memory; and transmitting the first data to a host memory buffer in the host device from the first buffer memory. The first data corresponds to at least a portion of a second data to be written to the second memory portion.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

Abstract: An optical mechanism is provided, including a base module, a ball element, and a movable module. The base module has a frame, a substrate movably disposed in the frame, and an image sensor disposed on the substrate. The ball element is disposed between the frame and the substrate, whereby the image sensor and the substrate are movable relative to the frame. The movable module is configured to hold an optical element and is movably connected to the base module.

Abstract: An assembling method for an optical system is provided, including: providing a first movable portion, connecting the first movable portion to a first fixed portion, providing a second movable portion, connecting the second movable portion to a second fixed portion, engaging the first fixed portion to the second fixed portion, adjusting the position of the first movable portion relative to the first fixed portion to a first predetermined position and temporarily affixing the first movable portion in the first predetermined position, affixing a first optical member to the first movable portion, and affixing a second optical member to the second movable portion.

Abstract: An optical mechanism is provided, including a base module, an optical element, and a ball element. The base module has a frame, a substrate movably disposed in the frame, and an image sensor disposed on the substrate. The optical element is movably connected to the base module, and light propagates through the optical element to the image sensor to generate a digital image. The ball element is disposed between the frame and the substrate, whereby the image sensor and the substrate are movable relative to the frame along a first axis that is perpendicular to an optical axis of the optical element.

Abstract: Provided are compositions and methods for selectively etching hard mask layers and/or photoresist etch residues relative to low-k dielectric layers that are present. More specifically, the present invention relates to a composition and process for selectively etching titanium nitride and/or photoresist etch residues relative to low-k dielectric layers. Other materials that may be present on the microelectronic device should not be substantially removed or corroded by said compositions.

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

Abstract: The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

Abstract: An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

Abstract: A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.

Abstract: An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target sub-mapping table corresponding to the data address has been cached, wherein the target sub-mapping table is one of the sub-mapping tables; and if false, reading and caching the target sub-mapping table from the sub-mapping tables.

Abstract: An example non-transitory computer-readable medium storing machine-readable instructions that, when executed by a processor, cause the processor to: set a graphical processing unit (GPU) power allocation, the GPU power allocation indicating power available for use by a GPU. The processor sets a processor power allocation, the processor power allocation indicating power available for use by the processor. The processor receives a GPU usage value and modifies the GPU power allocation to a modified GPU power allocation based on the GPU usage value. The processor modifies the processor power allocation to a modified processor power allocation based on the modification of the GPU power allocation.

Abstract: This application provides a structure of the optical sensor, in which a photosensitive element is arranged on a substrate, a colloid layer is arranged on the upper part of the substrate and covers the photosensitive element, and a thin film is further arranged. The device includes an adhesive layer and a light-transmitting layer, the adhesive layer is disposed above one of the colloid layers, the light-transmitting layer is disposed above one of the adhesive layers, and the structure can be used to provide the film member that can be changed according to requirements The optical design reduces the production cost of the optical sensor; this application further provides a shielding layer between the film member and the colloid layer to improve the photosensitive efficiency of the optical sensor.

Abstract: A plasticizer and a method for producing the same are provided. The method for producing the plasticizer includes: reacting a reaction mixture at each of a plurality of temperature holding stages in a heating process to form a semi-finished product; and purifying the semi-finished product at each of a plurality of low pressure stages of a decompression process to obtain a plasticizer. A temperature range of the heating process is from 140° C. to 220° C., a pressure range of the decompression process is from 750 Torr to 20 Torr, and the reaction mixture contains dibasic acid, diol, monohydric alcohol, and catalyst.

Abstract: A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.