Abstract: A thin film transistor liquid crystal display is designed such that TFTs for driving green pixels are formed in the blue pixel regions. This improves the overall brightness of the liquid crystal display based on the human view-sensitive characteristics.

Abstract: The disclosure concerns a pellet type LiF element for a thermoluminescent dosimetry (TLD) and its preparation. More particularly, the disclosure concerns the pellet type LiF element for a thermoluminescent dosimetry (TLD) which includes 0.35˜0.12% by mole of Mg source; 0.08˜0.001% by mole of Cu source; 1.3˜0.5% by mole of Na source; and 1.3˜0.5% by mole of Si source as dopants. The pellet type LiF element according to the present invention shows excellent sensitivity and has the preferred glow curve with a simple and single main peak.

Abstract: A method for fabrication a substrate for a liquid crystal display device includes: forming a color filter layer on a substrate; coating an organic layer on the color filter layer; irradiating a first light onto the organic layer; irradiating a second light onto the organic layer through a mask having a transmitting portion and a shielding portion, an energy density of the first light smaller than an energy density of the second light; and forming an overcoat layer and a column spacer by developing the organic layer.

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

Abstract: A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germanium layer thereon. A silicon-germanium epitaxial layer is formed on the porous silicon-germanium layer, an oxide layer is formed on a second silicon substrate, the second silicon substrate is bonded where the oxide layer is formed to the first silicon substrate where the silicon-germanium epitaxial layer is formed. Layers are removed to expose the silicon-germanium epitaxial layer and a strained silicon epitaxial layer is formed thereon. The porous silicon-germanium layer prevents lattice defects of the relaxed silicon-germanium layer from transferring to the silicon-germanium epitaxial layer. Therefore, it is possible to form the silicon-germanium layer and the strained silicon layer of the SOI layer without defects.

Abstract: A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

Abstract: Provided is a method for fabricating a semiconductor device. According to the method, an insolating layer which defines an active region on a semiconductor substrate is formed and a gate is formed on the active region of the semiconductor substrate. A first spacer layer which covers the gate and is extended to cover the isolating layer is formed as a first insulating material. A second spacer layer is formed on the first spacer layer as a second insulating material. A second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer is formed. A first spacer by a portion of the first spacer layer, which is protected by the second spacer by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, and a protection layer, which protects the insulating layer by remaining the portion of the first spacer of which thickness is reduced, are formed.

Abstract: A thin film transistor liquid crystal display is designed such that TFTs for driving green pixels are formed in the blue pixel regions. This improves the overall brightness of the liquid crystal display based on the human view-sensitive characteristics.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: An in-plane switching mode liquid crystal display device includes a plurality of gate lines and data lines defining a plurality of pixel regions, a driving device disposed within each of the pixel regions, at least one first electrode having a first width and at least one second electrode having a second width both arranged within the pixel region, and at least one third electrode having a third width overlapping at least one of the first and second electrodes to form a storage capacitor.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.

Abstract: A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

Abstract: Provided is a method for fabricating a semiconductor device. According to the method, an insolating layer which defines an active region on a semiconductor substrate is formed and a gate is formed on the active region of the semiconductor substrate. A first spacer layer which covers the gate and is extended to cover the isolating layer is formed as a first insulating material. A second spacer layer is formed on the first spacer layer as a second insulating material. A second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer is formed. A first spacer by a portion of the first spacer layer, which is protected by the second spacer by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, and a protection layer, which protects the insulating layer by remaining the portion of the first spacer of which thickness is reduced, are formed.

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

Abstract: A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

Abstract: A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

Abstract: A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.

Abstract: A liquid crystal display device includes an upper substrate, a lower substrate, a liquid crystal layer between the upper and lower substrates, a transparent electrode consisting of at least two layers of transparent material provided on at least one of the upper and lower substrates and a spacer material jetted onto the transparent electrode by an ink-jet system, wherein the spacer material has a hydrostatic property different from one of the at least two layers of the transparent electrode.

Abstract: The disclosure concerns a pellet type LiF element for a thermoluminescent dosimetry (TLD) and its preparation. More particularly, the disclosure concerns the pellet type LiF element for a thermoluminescent dosimetry (TLD) which includes 0.35˜0.12 % by mole of Mg source; 0.08˜0.001 % by mole of Cu source; 1.3˜0.5 % by mole of Na source; and 1.3˜0.5 % by mole of Si source as dopants. The pellet type LiF element according to the present invention shows excellent sensitivity and has the preferred glow curve with a simple and single main peak.