Patents by Inventor Jung Wang

Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040085084
    Abstract: A method and apparatus is provided for stress testing integrated circuits to determine their susceptibility to hot carrier charge injection damage. The system includes a hot carrier injection source formed on a semiconductor wafer carrying the ICs under test. The carrier source comprises an adjustable, voltage controlled oscillator having a variable frequency AC output test signal, and a modulator circuit for varying the duty cycle of the test signal applied to the ICs.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Jung Wang, Shih-Liang Wang, Chao-Hao Cheng
  • Publication number: 20040053142
    Abstract: A mask for defining a guard ring pattern. The mask includes a transparent substrate, a light-shielding layer, and at least one pair of assisted line patterns. The light-shielding layer is disposed on the transparent substrate and has a rectangular ring pattern composed of a plurality of opening patterns to define the guard ring pattern. The pair of assisted line patterns is parallelized by a predetermined interval on both sides of at least one section of the rectangular ring and have a predetermined width. Moreover, a method for defining a guard ring pattern is disclosed. First, a semiconductor substrate covered by an energy sensitive layer is provided. Next, photolithography is performed on the energy sensitive layer using the mask to transfer the guard ring pattern inside.
    Type: Application
    Filed: December 13, 2002
    Publication date: March 18, 2004
    Applicant: Nanya Technology Corporation
    Inventors: Hsien-Jung Wang, Yuan-Hsun Wu
  • Patent number: 6689913
    Abstract: Provided is a process for preparing terbinafine or its HCl salt comprising: reacting a furan derivative with a base to form a second compound; performing a reductive alkylation of the second compound obtained in the step with N-methyl-1-naphthalenemethylamine or its HCl salt to form a third compound; and purifying the third compound.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: February 10, 2004
    Assignee: Yuhan Corporation
    Inventors: Tai-Au Lee, Kyu-Jung Wang, Hong-Bae Kim, Kyoung-Chan Kwon, Chang-Hoe Ku
  • Publication number: 20040019796
    Abstract: A system and method for firmware authentication includes a first memory with the firmware embedded therein, a programmable microprocessor, and a microprocessor coupling the first memory and the programmable microprocessor. The firmware includes a first cryptographic algorithm unit. The programmable microprocessor includes a second memory for storing a second cryptographic algorithm unit. The microprocessor runs the first cryptographic algorithm unit and generates a first digital signature. The programmable microprocessor runs the second cryptographic algorithm unit and generates a second digital signature. The microprocessor then runs a verification of the first and the second digital signatures. If the first digital signature and the second digital signature are identical to each other, the authentication of the firmware is accomplished; otherwise, the system halts.
    Type: Application
    Filed: December 30, 2002
    Publication date: January 29, 2004
    Inventor: Hung-Jung Wang
  • Patent number: 6638871
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: October 28, 2003
    Assignee: United Microlectronics Corp.
    Inventors: Chin-Jung Wang, Tong-Yu Chen
  • Patent number: 6617180
    Abstract: A new method is provided for the interconnection of bit lines in the test structure. The invention provides for the creation of a cross comb bit line design in the test structure which allows for the detection and identification of diagonal or horizontal bridging between two identifiable capacitors of DRAM structures.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: September 9, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chien-Jung Wang
  • Patent number: 6605545
    Abstract: A method for forming hybrid low-k film stack is disclosed, in which an organic spin-on low-k material and CVD low-k material are combined to avoid thermal stress effect. This invention also provides a method for applying hybrid low-k film stack to dual damascene process.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: August 12, 2003
    Assignee: United Microelectronics Corp.
    Inventor: Chih-Jung Wang
  • Patent number: 6597589
    Abstract: A power converter, and more particularly a switched AC/DC converter, is provided with an input current shaping (ICS) function. The ICS function is carried out by adjusting the conducting angle of the input current for a rectifier coupled to a central tap of a main transformer, thereby obtaining a higher power factor. Owing to the action of the ICS, the ripples in the feedback signal are usually larger. The ripples are used to modulate the switching frequency to effectively disperse and planarize the electromagnetic energy distribution of the power supply, and to suppress the electromagnetic interference problems of the power supply.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: July 22, 2003
    Assignee: Delta Electronics, Inc.
    Inventor: Kuo-Jung Wang
  • Publication number: 20030129842
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.
    Type: Application
    Filed: January 10, 2002
    Publication date: July 10, 2003
    Inventors: Chin-Jung Wang, Tong-Yu Chen
  • Publication number: 20030129844
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
    Type: Application
    Filed: November 13, 2002
    Publication date: July 10, 2003
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Publication number: 20030130530
    Abstract: Provided are a process for preparing terbinafine or its HCl salt, which comprises: (a) reacting a furan derivative with a base; (b) performing a reductive alkylation of the resulting compound obtained in the step (a) with N-methyl-1-naphthalenemethylamine or its HCl salt; and (c) purifying the resulting compound obtained in the step (b).
    Type: Application
    Filed: December 27, 2002
    Publication date: July 10, 2003
    Inventors: Tai-Au Lee, Kyu-Jung Wang, Hong-Bae Kim, Kyoung-Chan Kwon, Chang-Hoe Ku
  • Publication number: 20030112642
    Abstract: A power converter, and more particularly a switched AC/DC converter provided with input current shaping (ICS) function is disclosed. The ICS function is carried out by adjusting the conducting angle of the input current for the rectifier in virtue of the central tap of the main transformer, and a higher power factor can be obtained. Owing to the action of the ICS, the ripples on the feedback signal are usually larger. The present invention uses the ripples to modulate the switching frequency to effectively disperse and planarize the electromagnetic energy distribution of the power supply, and obviate the electromagnetic interference deficiency of the power supply.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventor: Kuo-Jung Wang
  • Patent number: 6570760
    Abstract: A CPU cooling arrangement for portable computer is constructed to include a heat sink fastened to a CPU in a computer mainframe, the heat sink having two opposite open sides and a plurality of radiation fins defining a convection trough between each two adjacent radiation fins in communication with the open sides, a fan mounted in a fan hole on one sidewall of the computer mainframe, and a wing box coupled between the fan and one open side of the head sink.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: May 27, 2003
    Inventor: Jiung-Jung Wang
  • Publication number: 20030080368
    Abstract: A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second capacitor electrode has an area smaller than the first capacitor electrode. The passivation layer has an opening that exposes a portion of the second capacitor electrode. The pixel electrode layer and the second capacitor electrode are electrically connected through the opening in the passivation layer.
    Type: Application
    Filed: October 10, 2002
    Publication date: May 1, 2003
    Applicant: CHI MEI OPTOELECTRONICS CORPORATION
    Inventors: Yuan-Liang Wu, Tong-Jung Wang, Chin-Jung Kuo
  • Publication number: 20020182874
    Abstract: A method for forming hybrid low-k film stack is disclosed, in which an organic spin-on low-k material and CVD low-k material are combined to avoid thermal stress effect. This invention also provides a method for applying hybrid low-k film stack to dual damascene process.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Inventor: Chih-Jung Wang
  • Publication number: 20020122077
    Abstract: A method, apparatus, and article of manufacture for displaying the progress of a hierarchically structurable group of tasks is disclosed. The method comprises the steps of displaying a hierarchical representation of the group of tasks, delimiting a task in the group of tasks when the task has been processed, and displaying a processing result for the task in the hierarchical representation. In one embodiment, an icon is also displayed in the hierarchical representation to indicate whether the task completed normally or not. In another embodiment, the window displaying the progress of the hierarchically structured group of tasks further comprises an additional area to present additional information about the process, such as diagnostic information. The article of manufacture comprises a data storage device tangibly embodying instructions to perform the method steps described above.
    Type: Application
    Filed: December 29, 1998
    Publication date: September 5, 2002
    Inventors: GARY CHARLES DONEY, MICHAEL MORRIS GOLDING, SHU JUNG WANG
  • Publication number: 20020064919
    Abstract: A method for fabricating a gate, wherein a polysilicon gate is formed on a substrate. A first spacer is then formed on a sidewall of the polysilicon gate, while a second spacer is formed on the sidewall of the first spacer. The exposed part of the first spacer is partially removed by performing an anisotropic etching. The metal salicide is formed on the polysilicon gate and the exposed substrate.
    Type: Application
    Filed: June 18, 1999
    Publication date: May 30, 2002
    Inventor: CHIEN-JUNG WANG
  • Patent number: 6396751
    Abstract: A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: May 28, 2002
    Assignee: Taiwan Semiconductor Manufacturing Corporation, LTD
    Inventors: Yih-Yuh Doong, Tsu-bin Shen, Sung Chun Hsieh, Chien-Jung Wang
  • Publication number: 20010052274
    Abstract: An adjustable wrench includes a handle and a head extended from the handle. The head includes a fixed jaw, a movable jaw, and an adjusting screw. The movable jaw is rectilinearly movable relative to the fixed jaw upon rotation of the adjusting screw. A locking device is provided for locking the adjusting screw in place to thereby preventing rotation of the adjusting screw. A guide member is provided for guiding rectilinear movement of the movable jaw to thereby assure rectilinear movement of the movable jaw.
    Type: Application
    Filed: June 18, 2001
    Publication date: December 20, 2001
    Inventor: Mei-Jung Wang
  • Patent number: 6277742
    Abstract: A method of protecting a tungsten plug from corroding. After a tungsten plug is formed in a substrate, a wire is formed on the substrate to couple with the tungsten plug. The substrate is dipped into an electrolyte solution. The electrolyte solution is acid or alkaline enough to discharge charges accumulated on the wire. Then, a wet cleaning process is performed to remove polymer formed on the wire.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: August 21, 2001
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Jung Wang, Chingfu Lin, Lien-Jung Hung