Patents by Inventor Jung Wang

Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050201391
    Abstract: A network address translation (NAT)-enabled device such as a router or gateway device includes a NAT facility for connecting at least two hosts inside a first network to a second network allowing the inside hosts to share an address of the second network, a gateway interface for connecting to a demilitarized zone (DMZ) host inside the first network, a disposer connected to the gateway interface for assigning an address of the second network to the DMZ host, and a dispatcher connected to the gateway interface and the NAT facility for communicating messages between the second network and the gateway interface or the NAT facility according to a medium access control (MAC) address of the message.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 15, 2005
    Inventors: Hung-Fang Ma, Pau-Chuan Ting, Kuo-Chung Yu, Lun-Jung Wang
  • Publication number: 20050184324
    Abstract: A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second capacitor electrode has an area smaller than the first capacitor electrode. The passivation layer has an opening that exposes a portion of the second capacitor electrode. The pixel electrode layer and the second capacitor electrode are electrically connected through the opening in the passivation layer.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 25, 2005
    Inventors: Yuan-Liang Wu, Tong-Jung Wang, Chin-Jung Kuo
  • Patent number: 6934206
    Abstract: A new method is provided for the interconnection of bit lines in the test structure. The invention provides for the creation of a cross comb bit line design in the test structure which allows for the detection and identification of diagonal or horizontal bridging between two identifiable capacitors of DRAM structures.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: August 23, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chien-Jung Wang
  • Publication number: 20050110152
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
    Type: Application
    Filed: December 23, 2004
    Publication date: May 26, 2005
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Patent number: 6897475
    Abstract: This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying sizes, where adjacent ones of the plurality of first level bulk metals are coupled together using vias connected to second level thin conductors located therebetween. In addition, the test structure comprises a plurality of second level bulk metals having varying sizes, where adjacent ones of the plurality of second level bulk metals are coupled together using vias connected to first level thin conductors located therebetween. Furthermore, the test structure includes a first level contact pad coupled to a smallest of the plurality of second level bulk metals, and a second level contact pad coupled to a largest of the plurality of first level bulk metals. In such an embodiment, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: May 24, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Publication number: 20050094500
    Abstract: The specification disclosed a method that controls the access times of an optical disc and discs of the same. The method includes the following steps. First, an optical disc drive obtains the addresses of a life flag and a medium key block (MKB) by reading a private flag of an optical disc. The life flag and the MKB are used to control the access times of the optical disc. After confirming the addresses of the life flag and the MKB, the optical disc drive obtains an optical power signal to determine the power that should be used to read the MKB. When the optical disc drive uses the appropriate reading power to access the MKB, the recognizable number of access times in the MKB data is reduced, and the medium key signal is extracted to be confirmed if it is recognizable to restore the main data.
    Type: Application
    Filed: March 23, 2004
    Publication date: May 5, 2005
    Inventors: Guo-Zua Wu, Zu-Wen Chao, Yi-Jung Wang, Nai-Heng Tseng, Shu-Ching Chen
  • Patent number: 6887730
    Abstract: A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second capacitor electrode has an area smaller than the first capacitor electrode. The passivation layer has an opening that exposes a portion of the second capacitor electrode. The pixel electrode layer and the second capacitor electrode are electrically connected through the opening in the passivation layer.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 3, 2005
    Assignee: Chi Mei Optoelectronics Corporation
    Inventors: Yuan-Liang Wu, Tong-Jung Wang, Chin-Jung Kuo
  • Patent number: 6858355
    Abstract: A mask for defining a guard ring pattern. The mask includes a transparent substrate, a light-shielding layer, and at least one pair of assisted line patterns. The light-shielding layer is disposed on the transparent substrate and has a rectangular ring pattern composed of a plurality of opening patterns to define the guard ring pattern. The pair of assisted line patterns is parallelized by a predetermined interval on both sides of at least one section of the rectangular ring and have a predetermined width. Moreover, a method for defining a guard ring pattern is disclosed. First, a semiconductor substrate covered by an energy sensitive layer is provided. Next, photolithography is performed on the energy sensitive layer using the mask to transfer the guard ring pattern inside.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: February 22, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Hsien-Jung Wang, Yuan-Hsun Wu
  • Publication number: 20050024526
    Abstract: A multi-function portable disk includes a housing, a control unit, an image pick-up module and a display unit, wherein the control unit, the image pick-up module and the display unit are fixed in the housing. The control unit has a printed circuit board. There are a main memory element, electric components and a connector arranged on the printed circuit board. The image pick-up module includes a lens system and a viewfinder that connect with the printed circuit board. The display unit includes a display screen and a defensive glass. The portable disk has memory function and other functions, such as the function of digital camera, digital video/audio recorder, PC-camera or MP3 player.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Inventor: Mu-Jung Wang
  • Publication number: 20050023585
    Abstract: A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second capacitor electrode has an area smaller than the first capacitor electrode. The passivation layer has an opening that exposes a portion of the second capacitor electrode. The pixel electrode layer and the second capacitor electrode are electrically connected through the opening in the passivation layer.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 3, 2005
    Inventors: Yuan-Liang Wu, Tong-Jung Wang, Chin-Jung Kuo
  • Publication number: 20050018872
    Abstract: A watermark embedding method based on DCT subband image characters is disclosed. An original image is converted into a frequency image using a discrete cosine transformation. The watermark information is then embedded into a specific embedding block in each macro-block of the frequency image. The method has the following advantages: (1) the image embedded by watermark is resistant from distortion and damages from compressions; (2) the watermark image can be extracted without employing the original image; and (3) the quality of the image embedded with the watermark image can remain intact.
    Type: Application
    Filed: November 5, 2003
    Publication date: January 27, 2005
    Inventors: Guo-Zua Wu, Yi-Jung Wang, Zu-Wen Chao, Chwan-Chang Chen
  • Patent number: 6815715
    Abstract: A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second capacitor electrode has an area smaller than the first capacitor electrode. The passivation layer has an opening that exposes a portion of the second capacitor electrode. The pixel electrode layer and the second capacitor electrode are electrically connected through the opening in the passivation layer.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: November 9, 2004
    Assignee: Chi Mei Optoelectronics Corporation
    Inventors: Yuan-Liang Wu, Tong-Jung Wang, Chin-Jung Kuo
  • Patent number: 6815971
    Abstract: A method and apparatus is provided for stress testing integrated circuits to determine their susceptibility to hot carrier charge injection damage. The system includes a hot carrier injection source formed on a semiconductor wafer carrying the ICs under test. The carrier source comprises an adjustable, voltage controlled oscillator having a variable frequency AC output test signal, and a modulator circuit for varying the duty cycle of the test signal applied to the ICs.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: November 9, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chien-Jung Wang, Shih-Liang Wang, Chao-Hao Cheng
  • Publication number: 20040212726
    Abstract: An electronic image-capture module includes a flexible printed circuit board having an assembly section and a flat cable section which extends from the assembly section, the flat cable section having metal layers formed on both sides in order to prevent electric and magnetic interference (EMI); an image sensor mounted on the first side of the assembly section; a lens mounted on and aligned with the image sensor; an image processing IC mounted on the second side of the assembly section, the image sensor and the image processing IC being mounted on different sides of the assembly section; a connector assembled on the end of the flat cable section to connect to a printed circuit board of an electronic apparatus, such as digital camera; and a serial flash RAM mounted on the assembly section and connected to the image sensor for recording the deficient information, such as the white points, black points and color deviation, of the image sensor in order to have correction and compensation provided by the electronic
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Inventor: Mu-Jung Wang
  • Publication number: 20040207383
    Abstract: This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying sizes, where adjacent ones of the plurality of first level bulk metals are coupled together using vias connected to second level thin conductors located therebetween. In addition, the test structure comprises a plurality of second level bulk metals having varying sizes, where adjacent ones of the plurality of second level bulk metals are coupled together using vias connected to first level thin conductors located therebetween. Furthermore, the test structure includes a first level contact pad coupled to a smallest of the plurality of second level bulk metals, and a second level contact pad coupled to a largest of the plurality of first level bulk metals. In such an embodiment, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 21, 2004
    Inventor: Chien-Jung Wang
  • Publication number: 20040175478
    Abstract: The subject invention, therefore, comprises pasta noodles that have wheat grain and non-wheat grain in sufficient quantities as will form a matrix to provide the appropriate texture to the pasta noodles.
    Type: Application
    Filed: February 17, 2004
    Publication date: September 9, 2004
    Inventor: Shing-Jung Wang
  • Publication number: 20040175483
    Abstract: A dry flour composition is provided to be mixed with added water for forming dough. The flour composition includes a wheat flour component, and a non-wheat cereal component. The amount of the non-wheat cereal component is at least 30% by weight based on the total weight of the dry flour composition in the absence of added water. The dry flour composition contains an additive, which is selected from a group consisting of wheat gluten protein and Curdlan, in an amount sufficient to provide a net-like structure for the dough.
    Type: Application
    Filed: July 28, 2003
    Publication date: September 9, 2004
    Applicant: Standard Food Corporation
    Inventor: Shing-Jung Wang
  • Publication number: 20040153275
    Abstract: A new method is provided for the interconnection of bit lines in the test structure. The invention provides for the creation of a cross comb bit line design in the test structure which allows for the detection and identification of diagonal or horizontal bridging between two identifiable capacitors of DRAM structures.
    Type: Application
    Filed: July 24, 2003
    Publication date: August 5, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventor: Chien-Jung Wang
  • Publication number: 20040142608
    Abstract: A structure of a connector terminal is described. The structure of the connector terminal has a connecting end, a securing end and a plurality of neck sections disposed between the connecting end and the securing end such that a neck section can be cut to obtain a conductive terminal of desired length.
    Type: Application
    Filed: November 12, 2003
    Publication date: July 22, 2004
    Inventor: Pei-Jung Wang
  • Publication number: 20040099025
    Abstract: An anti-theft combination lock for car includes a main body having a transverse hole, a driving unit located at one side of the main body, a lock rod extended through the transverse hole of the main body, a lock plate fixedly connected at an end to a power output shaft of the driving unit to movably locate at an upper outer side of the transverse hole to normally engage with one of many annular retaining grooves on the lock rod to set the lock in a locked state. A password may be entered via an input interface provided on a top of an outer case of the main body. An internal memory processor determines the correctness of the entered password and actuates the driving unit to turn the lock plate to an unlock position when the entered password is correct.
    Type: Application
    Filed: October 31, 2003
    Publication date: May 27, 2004
    Inventor: Chi-Jung Wang