Patents by Inventor Junichi Sasaki

Junichi Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6393171
    Abstract: The integrity of a solder jointing pad, which is used to mount an optical module, is enhanced by avoiding exposure to high temperatures used in the formation of an accompanying optical wave guide. The enhanced integrity of the solder jointing pad permits a mounting solder bump to be evenly distributed on the pad, which improves mounting position characteristics. The solder jointing pads are elongated in shape and arranged in parallel and perpendicular orientation with respect to an optical transmission path in the optical module. The enhanced integrity of the solder jointing pads permits a precise amount of solder to be introduced to the pads when mounting the optical module. The optical module can then be precisely positioned simply by varying the amount of solder introduced to the solder jointing pads. The optical device can be positioned with high accuracy by taking advantage of the self-alignment action which occurs between the molten solder bumps and the solder jointing pads.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: May 21, 2002
    Assignee: NEC Corporation
    Inventors: Junichi Sasaki, Masataka Itoh, Naoki Kitamura
  • Patent number: 6383285
    Abstract: A simple and inexpensive method and apparatus for producing crystalline silicon comprising the steps of melting silicon in a mold, then cooling the bottom of the mold is cooled to create a positive temperature gradient from the bottom of the mold upward, thereby causing the molten silicon to crystallize from the inner bottom of the mold upward so that the solid-liquid phase boundary, separating the crystallized silicon from the molten silicon, moves upward as the molten silicon crystallizes. As the silicon crystallizes, an inert gas is blown onto the surface of the molten silicon from a position above the surface of the molten silicon, thereby vibrating the surface of the molten silicon in such a manner that cavities are formed in the surface of the molten silicon.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: May 7, 2002
    Assignee: Mitsubishi Materials Corporation
    Inventors: Saburo Wakita, Yoshinobu Nakada, Junichi Sasaki, Yuji Ishiwari
  • Publication number: 20010041034
    Abstract: The present invention provides a substrate, an optical fiber connecting end member, an optical element-housing member, a light module, and a manufacturing method of the substrate. The substrate has a feature that can be stably realizable and having a simple structure and that a light waveguide formed on the substrate surface or an optical element formed thereon can be connected without core alignment to an optical element provided on the optical fiber of the optical fiber connector to be connected to the optical fiber connecting end member. The substrate of the present invention is characterized in steps 5 for positioning being formed on at least one side of the substrate 1 that provides the optical waveguide 4.
    Type: Application
    Filed: May 10, 2001
    Publication date: November 15, 2001
    Inventors: Junichi Sasaki, Kazuhiko Kurata, Takanori Shimizu
  • Publication number: 20010033718
    Abstract: The integrity of a solder jointing pad, which is used to mount an optical module, is enhanced by avoiding exposure to high temperatures used in the formation of an accompanying optical wave guide. The enhanced integrity of the solder jointing pad permits a mounting solder bump to be evenly distributed on the pad, which improves mounting position characteristics. The solder jointing pads are elongated in shape and arranged in parallel and perpendicular orientation with respect to an optical transmission path in the optical module. The enhanced integrity of the solder jointing pads permits a precise amount of solder to be introduced to the pads when mounting the optical module. The optical module can then be precisely positioned simply by varying the amount of solder introduced to the solder jointing pads. The optical device can be positioned with high accuracy by taking advantage of the self-alignment action which occurs between the molten solder bumps and the solder jointing pads.
    Type: Application
    Filed: June 20, 2001
    Publication date: October 25, 2001
    Applicant: NEC Corporation
    Inventors: Junichi Sasaki, Masataka Itoh, Naoki Kitamura
  • Patent number: 6238100
    Abstract: A semiconductor optical amplifier is mounted on a substrate which is provided for a package. Fiber blocks in which plural parallel internal optical fibers are supported are fitted to the package. The optical fibers are optically coupled with the semiconductor optical amplifier via optical waveguides formed on the substrate. V grooves for supporting the optical fibers which protrude out from the fiber block are formed on the substrate. Positionings of the optical fibers are performed by fitting the fiber blocks to the package so that end faces of the optical fibers butt against end walls of the V grooves.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: May 29, 2001
    Assignee: NEC Corporation
    Inventors: Junichi Sasaki, Tomoaki Kato, Masataka Itoh
  • Patent number: 6115515
    Abstract: An optical device mounting board with electrodes mounted on the surface of the mounting board and separated from one another by grooves dividing the surface of the mounting board includes printed circuit boards having distribution lines for connecting the divided electrodes and spanning the grooves.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: September 5, 2000
    Assignee: NEC Corporation
    Inventors: Masataka Itoh, Junichi Sasaki
  • Patent number: 6053395
    Abstract: A method of bonding a chip element to a wafer-board through at least a solder bump having a surface coated with an oxide layer placed between the chip element and the wafer-board is provided. The method comprises the following steps. The oxide layer coating the surface of the solder bump is exposed to a liquid. An energy is given to the solder bump both for melting the solder bump and for causing at least one of a convection and a cavitation of at least an adjacent part of the liquid to the oxide layer, so as to allow the at least one of the convection and the cavitation to remove the oxide layer from the surface of the solder bump, whereby the solder bump bonds the chip element and the wafer-board.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: April 25, 2000
    Assignee: NEC Corporation
    Inventor: Junichi Sasaki
  • Patent number: 5929500
    Abstract: A light receiving element is comprised of a light sensitive surface on a semiconductor substrate and a positive electrode (anode), a negative electrode (cathode), a mounting precision test mask, a conductive electrode wire, and solder resist on the same substrate surface. A metal thin film, a mounting alignment mark, and a mounting precision mark window are provided on the back side of the substrate. Two or more electrode surfaces having either the anode or the cathode used as the common electrode are provided. The light sensitive surface is positioned approximately in the center between these two electrode surfaces. A highly precise mounting can therefore be achieved with the solder bump, even when mounting single light receiving elements. High precision mounting is also obtained when mounting light receiving element arrays. This type of light receiving element can be precisely positioned and bonded by solder bumps to a substrate having an optical fiber fitted in the V groove.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: July 27, 1999
    Assignee: NEC Corporation
    Inventors: Isao Yoneda, Kiyoshi Fukushima, Junichi Sasaki, Hiroshi Honmou, Masataka Itoh
  • Patent number: 5793914
    Abstract: An optical module and method in which an optical element (32) and an optical waveguide (34) are formed on a silicon substrate (31) so that an optical axis of the optical element coincides with an optical axis of the optical waveguide. Metallized films (41, 42) are formed on the silicon substrate and on the optical waveguide respectively, and these metallized films are bonded to each other by mutual diffusion of their atoms.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventor: Junichi Sasaki
  • Patent number: 5717803
    Abstract: The optical fibers are arranged in a V groove formed at the surface of a silicon substrate and a cover is provided thereon. An electrode for solder bump is respectively formed at the position opposed with each other to the substrate and cover. These substrate and cover are deposited with solder in order to fix the optical fibers. The substrate or cover is previously provided, at the end point part of the optical fibers, with the mark for the positioning in the longitudinal direction of the optical fibers. The optical fibers are positioned with this mark. Here, the side surface of the optical fibers is provided with the metallized area at the position located in the predetermined distance from the end point thereof. Before fixing with the cover, the optical fibers can be deposited automatically to the predetermined position without alignment due to the self-alignment effect between the mark and metallized area.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: February 10, 1998
    Assignee: Nec Corporation
    Inventors: Isao Yoneda, Junichi Sasaki, Masataka Itoh, Hiroshi Honmou
  • Patent number: 5573170
    Abstract: In an apparatus for punching a metallic sheet to stamp out a bump and bonding it to a substrate, an AuSn sheet is heated to above a softening point thereof by a heater. A solenoid is energized to cause a punch and a die to stamp out a bump from the AuSn sheet. The bump is directly bonded to a substrate. The punch is made up of a shank portion and a punch portion. A punch holder for guiding the shank portion and punch portion with high accuracy molded integrally with the die. The punch is connected to the solenoid with the intermediary of a damper spring. When the bump hits against the substrate, the damper spring prevents it from chipping off or cracking due to an impact. Subsequently, another solenoid is energized to move the punch further downward, thereby pressing the bump against the substrate for a sufficient period of time.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: November 12, 1996
    Assignee: NEC Corporation
    Inventors: Junichi Sasaki, Masataka Itoh, Hiroshi Honmou, . Yoshinobu Kaneyama
  • Patent number: 5513089
    Abstract: A switching power source control circuit comprising a comparator, a thin-out-processed pulse generator, a thinned-pulse detector, and a reset speed regulator, wherein: the comparator compares an output signal of an error amplifier with a variable reference voltage generated by the reference voltage regulator to generate a signal for performing thin-out operation in accordance with a voltage difference between the output signal of the error amplifier and the reference voltage; the thin-out-processed pulse generator generates thin-out-processed pulses on the basis of the output signal of the comparator; the thinned-out pulse detector detects the generation of thinned-out pulses or driving pulses while always monitoring the thin-out-processed pulses generated from the thin-out-processed pulse generator, and changes the reference voltage of the reference voltage regulator in the case where the thin-out rate is in a range of from 0 to 1/2 in the direction to make it difficult to perform thin-out operation to there
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: April 30, 1996
    Assignees: Hiyoshi Electric Works Co., Ltd., Micron Instrument Inc., Tohoku Ricoh Co., Ltd., Tsuneo Ikenoue
    Inventors: Sukehisa Sudo, Hitokatsu Hashimoto, Junichi Sasaki, Tsuneo Ikenoue
  • Patent number: 4608661
    Abstract: A hierarchy system constituted by a plurality of sequence controllers, each said controller having a central processing unit, a first memory unit for storing a system program, a second memory unit for storing a sequence program, a third memory unit for storing data required for performing the sequence program, an input control unit for controlling an input signal given from an input element, an output control unit for controlling an output signal to give to an output element, a bus line which connects with the central processing unit, the first memory unit, the second memory unit, and the input/output control units. Each controller has also a transmitting and a receiving unit for transferring to and receiving from other sequence controllers status signals. The system may connect the sequence controllers in a pyramid fashion in one embodiment of this invention. Some of the controllers have a plurality of receiving control units and transmitting control units.
    Type: Grant
    Filed: November 15, 1985
    Date of Patent: August 26, 1986
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventor: Junichi Sasaki
  • Patent number: 4550366
    Abstract: A programmable sequence controller and a sequence control system including a plurality of such controllers. Each sequence controller includes a program memory for storing a preprogrammed sequence of instructions for controlling a machine or part of a machine in response to the status of the machine or part being controlled. Each controller includes data transfer circuitry for receiving status data from another sequence controller on a common data bus and transmitting its own status data to all of the other sequence controllers on the common data bus. Each sequence controller includes an input-output (I/O) memory and an (I/O) flag memory for storing and keeping track of current status information from each of the plurality of controllers.
    Type: Grant
    Filed: August 12, 1982
    Date of Patent: October 29, 1985
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Fumiyasu Toyama, Masaaki Murakoshi, Masanori Wakuda, Junichi Sasaki, Hirotoshi Watanabe, Tomio Yukawa, Yoshihiko Okayama
  • Patent number: 4441161
    Abstract: A programmable sequence control apparatus including a first memory device for storing sequence program instructions, an input/output device, a relay ladder operation device for executing logic operations for a relay ladder circuit having n rows and m columns (wherein n and m are positive integers) in accordance with the program instructions, and a control device for delivering control signals to the relay ladder operation device, is so constructed that the control device includes a memory device for storing contact data and branch data for one column j (wherein j=1, 2, . . .
    Type: Grant
    Filed: April 9, 1981
    Date of Patent: April 3, 1984
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Junichi Sasaki, Yoshihiko Okayama
  • Patent number: D364395
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: November 21, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinichi Uratani, Junichi Sasaki