Abstract: A semiconductor structure is provided that includes a lateral passive diode co-integrated with nanosheet stacked FET technology. Notably, the semiconductor structure includes a passive/diode device region including a lateral passive diode that is located between two nanosheet stacks. In embodiments, a logic device region including a stacked nanosheet transistor is located adjacent to the passive/diode device region.

Abstract: A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) formed on a substrate and connected to a backside metal line of a backside power distribution network (BSPDN). The semiconductor device also includes a lateral junction diode co-integrated with the stacked nanosheet FET.

Abstract: A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

Abstract: A semiconductor structure is provided including stacked first and second devices wherein at least one of the stacked devices includes a lateral diode. The lateral diode includes a p-doped region as an anode, an n-doped region as a cathode and a semiconductor channel material region sandwiched between the anode and the cathode.

Abstract: A semiconductor structure is provided that includes a backside dielectric cap which seals the gate structure thus preventing gate structure exposure during backside processing. The presence of the backside dielectric cap helps to mitigate gate to direct backside source/drain contact shorts. The backside dielectric cap is formed during frontside processing.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor transistor on top of a substrate, the semiconductor transistor having a metal gate between a source region and a drain region, the metal gate having a top portion of a first length and a bottom portion of a second length measured in a direction from the source region to the drain region, wherein the first length of the top portion is shorter than the second length of the bottom portion. A method of forming the same is also provided.

Abstract: A microelectronic structure including a static random-access memory (SRAM) device that includes a plurality of stacked transistors. Each of the plurality of stacked transistors that includes a bottom transistor and an upper transistor, where the upper transistor is not in vertical alignment with the bottom transistor.

Abstract: A first VTFET is provided on a wafer. A second VTFET is adjacent to the first VTFET on the wafer. A backside power deliver network is on a backside of the wafer. A shared frontside contact is on a frontside of the wafer. The shared frontside contact is connected to a first top source/drain region of the first VTFET, a second top source/drain region of the second VTFET, and the backside power delivery network.

Abstract: Stacked field effect transistor (FET) static random access memory (SRAM) structures, circuits, and associated fabrication methods are presented. Recently there has been an emerging interest in considering stacked field effect transistor static random access memory bit-cell device designs that locate their pass-gate transistors on a top layer. This disclosure provides such designs. In particular, two x-couple implementations are presented that have their pass-gate transistors on a top layer. One implementation locates its x-couple between a top FET and a bottom FET. The other implementation locates its x-couple on the backside of the wafer.

Abstract: An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors in an upper semiconductor layer. The second plurality of vertical transport field-effect transistors is horizontally offset from the first plurality of vertical transport field-effect transistors by a horizontal distance that is one-half of a contacted gate pitch between adjacent vertical transport field-effect transistors in the same semiconductor layer.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice including a plurality of first upper transistors and a plurality of first lower transistors. The first nanodevice includes a first upper source/drain and a first lower source/drain that are offset from each other across the plurality of first upper transistors and the plurality of first lower transistors. The first upper source/drain includes a frontside surface and a backside surface and the first lower source/drain includes two separate horizontal frontside surfaces and a vertical inner sidewall. The vertical inner sidewall is located between the two separate horizontal frontside surfaces. A silicide layer is contiguous and conformal with the two separate horizontal frontside surfaces and the vertical inner sidewall.

Abstract: A microelectronic structure that includes a stack nanosheet transistor comprising a lower nanosheet transistor and an upper nanosheet transistor. The lower nanosheet transistor includes a lower source/drain and the upper nanosheet transistor includes an upper source/drain. An airgap located between the upper source/drain and the lower source/drain. The airgap is vertically aligned with the upper source/drain and the lower source/drain. A first layer located between the airgap and the lower source/drain.

Abstract: A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.

Abstract: A semiconductor device including a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is only in an edge cell of the logic block. A method including forming a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and edge cells surrounding the logic block, forming a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is in an edge cell of the logic block.

Abstract: The present disclosure describes a semiconductor IC device that includes a locally displaced to transistor active area. The locally displaced top active region may be associated with a top transistor that is stacked over the bottom transistor. The locally displaced top active region is offset or shifted with respect to the bottom active region and includes a displaced portion or region thereof that is offset or shifted to a lesser extent. For example, the top transistor active area may include a first portion that is laterally offset relative to the bottom active region by a first dimension and a locally displaced portion that is laterally offset relative to the bottom active region by a second dimension that is less than the first dimension. The displaced portion may allow adequate space for placement of a through interconnect without otherwise increasing an associated transistor horizontal cell dimension.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.

Abstract: A semiconductor device includes a first transistor device comprising a plurality of channel layers, one or more first spacers separating the plurality of channel layers, and a second spacer. The second spacer is disposed beneath the plurality of channel layers and has a width greater than that of the one or more first spacers.

Abstract: The present disclosure describes fabrication methods and resulting semiconductor integrated circuit (IC) devices that include a stacked transistor with an etch stop bonding structure. The etch stop bonding structure may provide etch stop protection, at least associated with the pre-clean etch and subsequent fabrication of an associated source/drain region of a top transistor. The etch stop bonding structure may protect against or prevent the associated fabricated source/drain region electrically shorting with an adjacent gate structure.

Abstract: A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided. The precision MOL resistor is located over a nanosheet device and is present in at least one resistor device region of a semiconductor substrate. The at least one resistor device region can include a first resistor device region in which the MOL resistor is optimized for low capacitance and/or a second resistor device region in which the MOL resistor is optimized for low self-heating.