Patents by Inventor Junli Wang

Junli Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250221028
    Abstract: Semiconductor devices and methods of forming the same include a bottom transistor having a bottom gate. A top transistor has a top gate above the bottom gate and is separated from the bottom transistor by a dielectric layer. A conductive via extends through the top gate and the dielectric layer to contact the bottom transistor. A dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Shay Reboh, Albert M. Chu, Junli Wang, Ruilong Xie
  • Publication number: 20250221029
    Abstract: Semiconductor devices includes a bottom field effect transistor (FET) over a substrate, having a bottom channel and bottom source/drain structures. A bottom plug of dielectric material penetrates the substrate and that makes contact with a channel of the bottom FET. A top FET over the bottom FET has a top channel that is laterally offset with respect to the bottom channel. Electrical contacts reach to the top FET and the bottom FET.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Shay Reboh, Ruilong Xie, Julien Frougier, Junli Wang, Tenko Yamashita
  • Patent number: 12349445
    Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: July 1, 2025
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Junli Wang, Teresa J. Wu, Tenko Yamashita
  • Patent number: 12349458
    Abstract: A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (Weff) Z, then the second logic cell has a height 2X, a width Y, and Weff>2.5 Z.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: July 1, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A Anderson, Junli Wang, Albert Chu
  • Patent number: 12342578
    Abstract: A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 24, 2025
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Albert M. Chu, Ruilong Xie, Junli Wang, Carl Radens
  • Publication number: 20250203946
    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked nanosheet structure and a second stacked nanosheet structure each including a first nanosheet structure formed at a first level and a second nanosheet structure formed at a second level. A configuration of the first stacked nanosheet structure on the first level is different than a configuration of the second stacked nanosheet structure on the first level, or the configuration of the first stacked nanosheet structure on the second level is different than a configuration of the second stacked nanosheet structure on the second level.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 19, 2025
    Inventors: Shay Reboh, Jay William Strane, Junli Wang, Chen Zhang, Brent A. Anderson
  • Publication number: 20250194242
    Abstract: A semiconductor structure is provided that includes a lateral passive diode co-integrated with nanosheet stacked FET technology. Notably, the semiconductor structure includes a passive/diode device region including a lateral passive diode that is located between two nanosheet stacks. In embodiments, a logic device region including a stacked nanosheet transistor is located adjacent to the passive/diode device region.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Shahrukh Khan, Biswanath Senapati, Utkarsh Bajpai, Chen Zhang, HUIMEI ZHOU, Junli Wang, Jay William Strane
  • Publication number: 20250192003
    Abstract: A semiconductor device is provided and includes a first transistor including a first source/drain (S/D) region, a second transistor stacked over the first transistor and including a second S/D region, a first backside power rail (BPR) disposed below the first transistor, a second BPR disposed below the first BPR, a via by which the second S/D region and the first BPR are connected and metallization. The metallization passes through and is insulated from the first BPR. The first S/D region and the second BPR are connected by the metallization.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Inventors: Ruilong Xie, Chen Zhang, Shahrukh Khan, Junli Wang
  • Publication number: 20250192048
    Abstract: A semiconductor structure is provided that includes a backside dielectric cap which seals the gate structure thus preventing gate structure exposure during backside processing. The presence of the backside dielectric cap helps to mitigate gate to direct backside source/drain contact shorts. The backside dielectric cap is formed during frontside processing.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 12, 2025
    Inventors: Chen Zhang, Ruilong Xie, Debarghya Sarkar, Junli Wang
  • Publication number: 20250194163
    Abstract: A semiconductor device includes a stacked transistor structure including a column having field effect transistors on two levels in the column, the two levels including a top tier and bottom tier. First channels of a field effect transistor are disposed on a first side of the column at the top tier and second channels of a second field effect transistor disposed on a second side of the column opposite the first side at the bottom tier to form an offset between the first channels and the second channels within the column.
    Type: Application
    Filed: December 11, 2023
    Publication date: June 12, 2025
    Inventors: Shay Reboh, Albert M. Chu, Junli Wang, Brent A. Anderson
  • Publication number: 20250185355
    Abstract: A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers and a first interfacial layer surrounding each of the plurality of first nanosheet channel layers, the first interfacial layer having a first thickness, and a second nanosheet field-effect transistor device vertically stacked above the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers and a second interfacial layer surrounding each of the plurality of second nanosheet channel layers, the second interfacial layer having a second thickness greater than the first thickness. A distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 5, 2025
    Inventors: Debarghya Sarkar, Takashi Ando, Abir Shadman, Shay Reboh, Junli Wang, Paul Charles Jamison
  • Publication number: 20250185361
    Abstract: Embodiments of the disclosure are directed to an integrated circuit (IC) that includes a bottom device and a top device positioned over the bottom device. The top device includes a first nanosheet and a second nanosheet. The bottom device includes a third nanosheet and a fourth nanosheet. A space between the first nanosheet and the second nanosheet is greater than a space between the third nanosheet and the fourth nanosheet.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 5, 2025
    Inventors: Chen Zhang, Ruilong Xie, Shay Reboh, Junli Wang
  • Patent number: 12317537
    Abstract: A semiconductor device is provided that includes a local passthrough interconnect structure present in a non-active device region of the device. A dielectric fill material structure is located between the local passthrough interconnect structure and a functional gate structure that is present in an active device region that is laterally adjacent to the non-active device region. The semiconductor device has reduced capacitance (and thus circuit speed is not compromised) as compared to an equivalent device in which a metal-containing sacrificial gate structure is used instead of the dielectric fill material structure.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: May 27, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Dechao Guo, Junli Wang, Alexander Reznicek
  • Publication number: 20250151342
    Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first group of field-effect-transistors (FETs); a second group of FETs on top of the first group of FETs; a first half-single-diffusion-break (H-SDB) underneath and being separated from one of the FETs of the second group by a middle-dielectric-insulator (MDI) layer; and a second H-SDB on top of and being separated from one of the FETs of the first group by the MDI layer, where the first H-SDB insulates a source/drain (S/D) region of a first FET of the first group of FETs from a S/D region of a second FET of the first group of FETs, and the second H-SDB insulates a S/D region of a first FET of the second group of FETs from a S/D region of a second FET of the second group of FETs. A method of forming the same is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Inventors: Chen Zhang, Ruilong Xie, Shay Reboh, Junli Wang
  • Patent number: 12278237
    Abstract: A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: April 15, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Junli Wang, Dechao Guo, Ruqiang Bao, Rishikesh Krishnan, Balasubramanian S. Pranatharthiharan
  • Patent number: 12278184
    Abstract: Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: April 15, 2025
    Assignee: International Business Machines Corporation
    Inventors: Albert M Chu, Junli Wang, Albert M. Young, Dechao Guo
  • Publication number: 20250118630
    Abstract: A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Ruilong Xie, Junli Wang, Kisik Choi, Koichi Motoyama, Nicholas Anthony Lanzillo, Biswanath Senapati, Albert M. Chu, Brent A. Anderson, Chen Zhang, Tenko Yamashita
  • Patent number: 12272648
    Abstract: A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source/drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: April 8, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Junli Wang, Julien Frougier, Dechao Guo, Lawrence A. Clevenger
  • Publication number: 20250113560
    Abstract: A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Lijuan Zou, Jay William Strane, Junli Wang, Brent A. Anderson, Ruilong Xie, Albert M. Chu
  • Patent number: 12268016
    Abstract: A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 1, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Junli Wang, Brent A Anderson, Chen Zhang, Heng Wu, Alexander Reznicek