Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice including a plurality of first upper transistors and a plurality of first lower transistors. The first nanodevice includes a first upper source/drain and a first lower source/drain that are offset from each other across the plurality of first upper transistors and the plurality of first lower transistors. The first upper source/drain includes a frontside surface and a backside surface and the first lower source/drain includes two separate horizontal frontside surfaces and a vertical inner sidewall. The vertical inner sidewall is located between the two separate horizontal frontside surfaces. A silicide layer is contiguous and conformal with the two separate horizontal frontside surfaces and the vertical inner sidewall.

Abstract: A microelectronic structure that includes a stack nanosheet transistor comprising a lower nanosheet transistor and an upper nanosheet transistor. The lower nanosheet transistor includes a lower source/drain and the upper nanosheet transistor includes an upper source/drain. An airgap located between the upper source/drain and the lower source/drain. The airgap is vertically aligned with the upper source/drain and the lower source/drain. A first layer located between the airgap and the lower source/drain.

Abstract: A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.

Abstract: A semiconductor device including a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is only in an edge cell of the logic block. A method including forming a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and edge cells surrounding the logic block, forming a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is in an edge cell of the logic block.

Abstract: The present disclosure describes a semiconductor IC device that includes a locally displaced to transistor active area. The locally displaced top active region may be associated with a top transistor that is stacked over the bottom transistor. The locally displaced top active region is offset or shifted with respect to the bottom active region and includes a displaced portion or region thereof that is offset or shifted to a lesser extent. For example, the top transistor active area may include a first portion that is laterally offset relative to the bottom active region by a first dimension and a locally displaced portion that is laterally offset relative to the bottom active region by a second dimension that is less than the first dimension. The displaced portion may allow adequate space for placement of a through interconnect without otherwise increasing an associated transistor horizontal cell dimension.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.

Abstract: A semiconductor device includes a first transistor device comprising a plurality of channel layers, one or more first spacers separating the plurality of channel layers, and a second spacer. The second spacer is disposed beneath the plurality of channel layers and has a width greater than that of the one or more first spacers.

Abstract: The present disclosure describes fabrication methods and resulting semiconductor integrated circuit (IC) devices that include a stacked transistor with an etch stop bonding structure. The etch stop bonding structure may provide etch stop protection, at least associated with the pre-clean etch and subsequent fabrication of an associated source/drain region of a top transistor. The etch stop bonding structure may protect against or prevent the associated fabricated source/drain region electrically shorting with an adjacent gate structure.

Abstract: A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided. The precision MOL resistor is located over a nanosheet device and is present in at least one resistor device region of a semiconductor substrate. The at least one resistor device region can include a first resistor device region in which the MOL resistor is optimized for low capacitance and/or a second resistor device region in which the MOL resistor is optimized for low self-heating.

Abstract: Semiconductor devices includes a bottom field effect transistor (FET) over a substrate, having a bottom channel and bottom source/drain structures. A bottom plug of dielectric material penetrates the substrate and that makes contact with a channel of the bottom FET. A top FET over the bottom FET has a top channel that is laterally offset with respect to the bottom channel. Electrical contacts reach to the top FET and the bottom FET.

Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer that includes a first transistor device. A first back-end-of-line (BEOL) layer is on a front side of the FEOL layer and includes a first electrical connection to the first transistor device. A second BEOL layer is on a back side of the FEOL layer and includes a first BEOL device with a second electrical connection to the first transistor device.

Abstract: A semiconductor device including a first pair of stacked transistors having a first upper transistor and a first lower transistor, a second pair of stacked transistors comprising a second upper transistor and a second lower transistor, and a first cross-connection between the first upper transistor and the second lower transistor.

Abstract: A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.

Abstract: A semiconductor structure including a reliable power rail in stacked field effect transistor technology with unequal device footprints is provided that mitigates, and in some cases even eliminates, shorting risks that are typically associated using long bars in advanced logic applications.

Abstract: Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form an extended-gate field effect transistor (EG-FET) on a substrate. The fabrication operations include forming a channel in an EG region of the substrate. A first EG gate dielectric is deposited over the channel at a first low-temperature. A reinforcement treatment is applied to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric. The first low-temperature is selected to be below the second low-temperature; and the second low-temperature is selected to be below a third low-temperature that causes a diffusion of a first type of semiconductor material across an interface and into a second type of semiconductor to exceed a predetermined minimum diffusion level or rate.

Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a second transistor, vertically stacked on the first transistor, including a second source/drain region. The semiconductor device includes an isolation layer positioned between the first transistor and the second transistor and an air gap positioned between the first source/drain region and the isolation layer.

Abstract: An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.