Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first group of field-effect-transistors (FETs); a second group of FETs on top of the first group of FETs; a first half-single-diffusion-break (H-SDB) underneath and being separated from one of the FETs of the second group by a middle-dielectric-insulator (MDI) layer; and a second H-SDB on top of and being separated from one of the FETs of the first group by the MDI layer, where the first H-SDB insulates a source/drain (S/D) region of a first FET of the first group of FETs from a S/D region of a second FET of the first group of FETs, and the second H-SDB insulates a S/D region of a first FET of the second group of FETs from a S/D region of a second FET of the second group of FETs. A method of forming the same is also provided.

Abstract: Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.

Abstract: A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

Abstract: A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels.

Abstract: A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source/drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.

Abstract: A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

Abstract: A semiconductor structure may include a first pass gate oriented along a first line. A semiconductor structure may include a first inverter in line with the first line. The first inverter may include a first channel region, a second channel region stacked above the first channel region. The semiconductor structure may also include an inverter gate around the first channel region and the second channel region, with a gate extension above the pass gate.

Abstract: A semiconductor device includes a top side and a bottom side opposite the top side. A central portion including a semiconductor substrate is disposed between the top side and the bottom side. A component is disposed in the central portion in contact with the semiconductor substrate. The component includes a first electrical connection from the top side and a second electrical connection from the bottom side.

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and bottom side. Active regions are disposed on the bottom side. The active regions include a recessed portion therein. A metal cap is disposed within the recessed portion. A contact is disposed within the metal cap to reduce contact resistance.

Abstract: A semiconductor device including stacked field effect transistors (FETs) is provided. The stacked FETs are formed utilizing a process that optimizes the thermal budget without negatively impacting the frontside and/or backside contact structures. The stacked can be designed to have different work function metals and a frontside/backside deep via structure can be provided that has a low area resistance.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.

Abstract: A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

Abstract: A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a protection diode. The protection diode includes a substrate, a gate, a first nanosheet layer, and a second nanosheet layer. The first nanosheet layer includes a heavily doped n-type epitaxial disposed over the substrate. Additionally, the first nanosheet layer is in contact with the gate. Further, the second nanosheet layer includes a heavily doped p-type epitaxial disposed over the substrate. Additionally, the second nanosheet layer is in contact with the gate. Further, the first nanosheet layer and the second nanosheet layer surround the gate.

Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.