Abstract: An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.

Abstract: A semiconductor device including a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate toward the first pair of stacked transistors, a cross-connection disposed in contact with the gate portion and extending upward, and a gate contact disposed in contact with the cross-connection and a top surface of the first upper transistor.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A p-channel field-effect transistor (pFET) having a source/drain region is formed, where: a bottom surface of the source/drain region is of a depth lower than a bottom surface of a gate region; and the source/drain region comprises a silicon germanium alloy doped with boron; An n-channel field-effect transistor (nFET) is formed. A via is formed, where the via has a top surface above a top surface of the nFET. The semiconductor structure is flipped. A substrate is selectively removed respective to the source/drain region. A backside interlayer dielectric (ILD) is formed, where the backside ILD is of a different material than a shallow trench isolation layer. A backside contact is formed, where the backside contact contacts the source/drain region and the via.

Abstract: Aspects of the invention are directed to fabrication methods and resulting structures for providing transistors having hybrid crystal orientation channels and mixed crystal orientation bottom epitaxies. In a non-limiting embodiment, a first fin having a first crystal orientation is formed in a first region of a substrate having a second crystal orientation. A second fin having the second crystal orientation is formed in a second region of the substrate. The second fin is formed directly on a surface of the substrate. A mixed crystal bottom source or drain region is formed between the first fin and the first region of the substrate and a single crystal bottom source or drain region having the second crystal orientation is formed on sidewalls of the second fin and on the surface of the substrate in the second region.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first top transistor comprising a first source/drain (S/D) region and a first bottom transistor with a second S/D region. The first bottom transistor may be stacked directly below the first transistor. The semiconductor structure may also include a backside power delivery network (BSPDN) below the bottom transistor, a back-end-of-line (BEOL) metal level above the top transistor, and a first interlevel via electrically connecting a top of the first S/D region to the BSPDN.

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Abstract: A microelectronic structure that includes a stacked FET that includes an upper FET and a lower FET, wherein the upper FET includes a NFET source/drain and the lower FET includes a PFET source/drain, wherein the PFET source/drain extends past a backside surface of a lower gate of the lower FET into a backside region of the stacked FET. A first backside interlayer dielectric layer located adjacent to a sidewall of the PFET source/drain that extends into the backside region. A second backside interlayer dielectric layer located on a backside surface of the first backside interlayer dielectric layer. A backside contact located on a backside surface of the PFET source/drain.

Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

Abstract: A device includes a base layer structure including a first region and a second region; a first bottom gate material in a plurality of first-type doped regions in the first and second regions; a second bottom gate material in a second-type doped regions in the first and second regions; first nanosheet gate-all-round device structures on the first bottom gate material; and second nanosheet gate-all-round device structures on the second bottom gate material, wherein the first bottom gate material is located over the second nanosheet gate-all-around device structures in the second-type doped regions of the first and second regions, wherein the second bottom gate material extends, in boundary regions between the first-type and second-type doped regions, on the base layer structure from the second nanosheet gate-all-around devices structures toward the first gate-all-round device structures.

Abstract: A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.

Abstract: Bonded stacked FETs with individually tunable gate dielectrics are provided. In one aspect, a stacked FET device includes: a bottom transistor disposed on a wafer; and a top transistor bonded on top of the bottom transistor via a bonding layer, where the bottom transistor includes a stack of first active layers, a first gate dielectric disposed on the first active layers, and a first gate electrode disposed on the first gate dielectric, where the top transistor includes a stack of second active layers, a second gate dielectric disposed on the second active layers, and a second gate electrode disposed on the second gate dielectric, and where the first gate dielectric has at least one of a different composition and a different thickness from the second gate dielectric. A method of forming the present stacked FET devices is also provided.

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

Abstract: A semiconductor device includes first and second source/drain regions, where the first source/drain region is at least partially laterally offset from the second source/drain region. The semiconductor device includes a first interlayer via extending into at least a portion of the first source/drain region, where the first interlayer via is isolated from the first source/drain region by a first dielectric liner, and a second interlayer via connected to the second source/drain region and to the first interlayer via, where the second interlayer via extends into at least a portion of the second source/drain region. The semiconductor device also includes a frontside contact connected to the first source/drain region, where the frontside contact is adjacent to, and isolated from, the second interlayer via.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: A method of fabrication a semiconductor device includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.

Abstract: A semiconductor device includes an input/output device including: a top transistor having a top source region and top drain region and a bottom transistor comprising a bottom source region and a bottom drain region. The top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region.

Abstract: A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.

Abstract: A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

Abstract: A vertically stacked 3D nanosheet field effect transistor component includes a bottom nanosheet device, a middle dielectric isolation region coupled to the bottom nanosheet device, and a top nanosheet device coupled to the middle dielectric isolation region. The middle dielectric isolation region can include at least one embedded stressor mechanically coupled to at least one of the bottom nanosheet device and the top nanosheet device that imparts an embedded stressor originated stress in at least one of the bottom nanosheet device and the top nanosheet device. At least one of the bottom nanosheet device and the top nanosheet device include at least one interlayer originated stress. The stress(es) impart device performance boost(s) for at least one of the bottom nanosheet device and the top nanosheet device.