Patents by Inventor Justin K. Brask

Justin K. Brask has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making a semiconductor device having a high-K gate dielectric and a titanium carbide gate electrode
    Patent number: 7317231
    Abstract: A method for making a titanium carbide layer is described. That method comprises alternately introducing a carbon containing precursor and a titanium containing precursor into a chemical vapor deposition reactor, while a substrate is maintained at a selected temperature. The reactor is operated for a sufficient time, and pulse times are selected for the carbon containing precursor and the titanium containing precursor, to form a titanium carbide layer of a desired thickness and workfunction on the substrate.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Suman Datta, Mark L. Doczy, Jack Kavalieros, Justin K. Brask, Robert S. Chau
  • Integrating n-type and p-type metal gate transistors
    Patent number: 7316949
    Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventors: Mark Doczy, Justin K. Brask, Steven J. Keating, Chris E. Barns, Brian S. Doyle, Michael L. McSwiney, Jack T. Kavalieros, John P. Barnak
  • Block contact architectures for nanoscale channel transistors
    Patent number: 7279375
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
  • Etch stop and hard mask film property matching to enable improved replacement metal gate process
    Patent number: 7271045
    Abstract: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Matthew J. Prince, Chris E. Barns, Justin K. Brask
  • Method of smoothing waveguide structures
    Patent number: 7262140
    Abstract: A semiconductor based structure containing substantially smoothed waveguides having a rounded surface is disclosed, as well as methods of fabricating such a structure. The substantially smoothed waveguides may be formed of waveguide materials such as amorphous silicon or stoichiometric silicon nitride. The substantially smoothed waveguides are formed with an isotropic wet etch combined with sonic energy.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Bruce A. Block
  • Method of varying etch selectivities of a film
    Patent number: 7247578
    Abstract: A method of patterning a crystalline film. A crystalline film having a degenerate lattice comprising first atoms in a first region and a second region is provided. Dopants are substituted for said first atoms in said first region to form a non-degenerate crystalline film in said first region. The first region and the second region are exposed to a wet etchant wherein the wet etchant etches the degenerate lattice in said second region without etching the non-degenerate lattice in the first region.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventor: Justin K. Brask
  • Device with scavenging spacer layer
    Patent number: 7226831
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Mark L. Doczy, Justin K. Brask, Robert S. Chau
  • Fabricating strained channel epitaxial source/drain transistors
    Patent number: 7226842
    Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Justin K. Brask, Andrew N. Westmeyer, Boyan Boyanov, Nick Lindert
  • Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer
    Patent number: 7220635
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Uday Shah, Matthew V. Metz, Chris E. Barns, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Methods for integrating replacement metal gate structures
    Patent number: 7217611
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Scott A. Hareland, Matthew V. Metz, Chris E. Barns, Robert S. Chau
  • Replacement gate process for making a semiconductor device that includes a metal gate electrode
    Patent number: 7208361
    Abstract: A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is wider than its lower surface. The method may be applied, when using a replacement gate process to make transistors that have metal gate electrodes.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Uday Shah, Chris E. Barns, Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Robert S. Chau
  • Forming dual metal complementary metal oxide semiconductor integrated circuits
    Patent number: 7192856
    Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: March 20, 2007
    Assignee: Intel Corporation
    Inventors: Mark Doczy, Lawrence D. Wong, Valery M. Dubin, Justin K. Brask, Jack Kavalieros, Suman Datta, Matthew V. Metz, Robert S. Chau
  • Depositing an oxide
    Patent number: 7192890
    Abstract: A dielectric deposited on a substrate may be exposed to a salt solution. While exposed to the salt solution, an oxide is deposited on the dielectric.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: March 20, 2007
    Assignee: Intel Corporation
    Inventors: Ying Zhou, Matthew V. Metz, Justin K. Brask, John Burghard, Markus Kuhn, Suman Datta, Robert S. Chau
  • Method for making a semiconductor device that includes a metal gate electrode
    Patent number: 7183184
    Abstract: A method for making a semiconductor device is described. That method comprises forming a hard mask and an etch stop layer on a patterned sacrificial gate electrode layer. After first and second spacers are formed on opposite sides of that patterned sacrificial layer, the patterned sacrificial layer is removed to generate a trench that is positioned between the first and second spacers. At least part of the trench is filled with a metal layer.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Chris E. Barns, Robert S. Chau
  • Method for making a semiconductor device that includes a metal gate electrode
    Patent number: 7176090
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Brian S. Doyle, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7160779
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Jack Kavalieros, Justin K. Brask, Matthew V. Metz, Suman Datta, Brian S. Doyle, Robert S. Chau
  • Method for making a semiconductor device that includes a metal gate electrode
    Patent number: 7160767
    Abstract: A method for making a semiconductor device is described. That method comprises forming a dummy dielectric layer that is at least about 10 angstroms thick on a substrate, and forming a sacrificial layer on the dummy dielectric layer. After removing the sacrificial layer and the dummy dielectric layer to generate a trench that is positioned between first and second spacers, a gate dielectric layer is formed on the substrate at the bottom of the trench, and a metal layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7157378
    Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Chris E. Barns, Mark L. Doczy, Uday Shah, Jack Kavalieros, Matthew V. Metz, Suman Datta, Anne E. Miller, Robert S. Chau
  • CMOS device with metal and silicide gate electrodes and a method for making it
    Patent number: 7153734
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7153784
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. Chau