Abstract: A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a narrow section, each pair being located at a different height of the silicon body. The silicon body is surrounded by a gate material on three sides. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The MBT-FET combines the advantages of a wide fin device and a narrow fin device.

Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

Abstract: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.

Abstract: Embodiments of the present invention describe a method of forming a multi-cornered film. According to the embodiments of the present invention, a photoresist mask is formed on a hard mask film formed on a film. The hard mask film is then patterned in alignment with the photoresist mask to produce a hard mask. The width of the photoresist mask is then reduced to form a reduced width photoresist mask. A first portion of the film is then etched in alignment with the hard mask. The hard mask is then etched in alignment with the reduced width photoresist mask to form a reduced width hard mask. A second portion of the film is then etched in alignment with the reduced width hard mask.

Abstract: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.

Abstract: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.

Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface.

Abstract: A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.

Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming at least one metal source/drain on a gate dielectric, wherein the at least one metal source/drain is adjacent to a channel region, wherein the channel region comprises at least one carbon nanotube.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Abstract: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.