Patents by Inventor Justin K. Brask

Justin K. Brask has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FORMING INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATE ELECTRODES
    Publication number: 20100219456
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 2, 2010
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7785958
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
  • Preventing silicide formation at the gate electrode in a replacement metal gate technology
    Patent number: 7754552
    Abstract: A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the polysilicon gate structure 14 from the formation of silicide or etch byproducts. Either the silicide or the etch byproducts or their combination may block the ensuing polysilicon etch which is needed to remove the polysilicon gate structure and to thereafter replace it with an appropriate metal gate technology.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: Chris E. Barns, Justin K. Brask, Mark Doczy
  • FORMING ABRUPT SOURCE DRAIN METAL GATE TRANSISTORS
    Publication number: 20100151669
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Lateral undercut of metal gate in SOI device
    Patent number: 7736956
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy, Robert S. Chau
  • Forming integrated circuits with replacement metal gate electrodes
    Patent number: 7718479
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7709909
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau
  • Method of forming abrupt source drain metal gate transistors
    Patent number: 7704833
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode
    Patent number: 7671471
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. Chau
  • FIELD EFFECT TRANSISTOR WITH METAL SOURCE/DRAIN REGIONS
    Publication number: 20090325350
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Application
    Filed: May 2, 2008
    Publication date: December 31, 2009
    Inventors: Marko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. Chau
  • Tensile Strained NMOS Transistor Using Group III-N Source/Drain Regions
    Publication number: 20090302350
    Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
    Type: Application
    Filed: August 14, 2009
    Publication date: December 10, 2009
    Inventors: Suman Datta, Justin K. Brask, Been-Yih Jin, Jack T. Kavalieros, Mantu K. Hudait
  • CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT
    Publication number: 20090280608
    Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Application
    Filed: November 2, 2006
    Publication date: November 12, 2009
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Forming high-k dielectric layers on smooth substrates
    Patent number: 7615441
    Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Gilbert Dewey, Robert S. Chau
  • Complementary Metal Oxide Semiconductor Integrated Circuit Using Raised Source Drain and Replacement Metal Gate
    Publication number: 20090261391
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Inventors: Jack KAVALIEROS, Annalisa CAPPELLANI, Justin K. BRASK, Mark L. DOCZY, Matthew V. METZ, Suman DATTA, Chris E. BARNS, Robert S. CHAU
  • Angled implantation for removal of thin film layers
    Patent number: 7595248
    Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: September 29, 2009
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Justin K. Brask, Justin S. Sandford, Jack Kavalieros, Matthew V. Metz
  • Tensile strained NMOS transistor using group III-N source/drain regions
    Patent number: 7592213
    Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 22, 2009
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Been-Yih Jin, Jack T. Kavalieros, Mantu K. Hudait
  • Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
    Publication number: 20090230480
    Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
    Type: Application
    Filed: May 26, 2009
    Publication date: September 17, 2009
    Inventors: Lucian Shifren, Jack T. Kavalieros, Steven M. Cea, Cory E. Weber, Justin K. Brask
  • SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
    Publication number: 20090218603
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Application
    Filed: May 8, 2009
    Publication date: September 3, 2009
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • Method of patterning a film
    Patent number: 7579280
    Abstract: A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Doyle, Uday Shah, Robert S. Chau
  • Removing a high-k gate dielectric
    Patent number: 7575991
    Abstract: A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 18, 2009
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Robert L. Norman, Justin K. Brask, Jack Kavalieros, Matthew Metz, Suman Datta, Robert S. Chau