Patents by Inventor Justin K. Brask

Justin K. Brask has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    Patent number: 7569443
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Chris E. Barns, Robert S. Chau
  • Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
    Patent number: 7566605
    Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventors: Lucian Shifren, Jack T. Kavalieros, Steven M. Cea, Cory E. Weber, Justin K. Brask
  • METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC
    Publication number: 20090179282
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
    Type: Application
    Filed: January 14, 2009
    Publication date: July 16, 2009
    Inventors: Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Matthew V. Mertz, Mark L. Doczy, Suman Datta, Robert S. Chau
  • Reducing Ambipolar Conduction in Carbon Nanotube Transistors
    Publication number: 20090159872
    Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.
    Type: Application
    Filed: January 26, 2009
    Publication date: June 25, 2009
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Marko Radosavljevic, Amlan Majumdar, Justin K. Brask, Robert S. Chau
  • Nonplanar device with thinned lower body portion and method of fabrication
    Patent number: 7550333
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: June 23, 2009
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • Selective surface exposure, cleans and conditioning of the germanium film in a Ge photodetector
    Patent number: 7547639
    Abstract: A method of protecting a sensitive layer from harsh chemistries. The method includes forming a first sensitive layer, forming a second layer upon the first layer, then forming a third layer over the second layer. The third layer is utilized as a mask during patterning of the second layer. During patterning, however, the second layer is only partially etched, thus leaving a buffer layer overlying the first layer. The third layer is completely removed while the buffer layer protects the first layer from the harsh chemicals that are utilized to remove the third layer. Then, the buffer layer is carefully removed down to the surface of the first layer.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: June 16, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Bruce A. Block, Uday Shah
  • Methods for patterning a semiconductor film
    Patent number: 7547637
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: June 16, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • METHOD OF FORMING A NONPLANAR TRANSISTOR WITH SIDEWALL SPACERS
    Publication number: 20090149012
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: February 11, 2009
    Publication date: June 11, 2009
    Inventors: Justin K. Brask, Brian S. Doyle, Jack Kavalieros, Mark Doczy, Uday Shah, Robert S. Chau
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20090142897
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 4, 2009
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • GATE ELECTRODE HAVING A CAPPING LAYER
    Publication number: 20090121297
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Application
    Filed: January 15, 2009
    Publication date: May 14, 2009
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material
    Patent number: 7531437
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Doyle, Jack Kavalieros, Mark Doczy, Uday Shah, Robert S. Chau
  • Nonplanar transistors with metal gate electrodes
    Patent number: 7528025
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 5, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Dovle, Jack Kavalleros, Mark Doczy, Uday Shah, Robert S. Chau
  • Gate electrode having a capping layer
    Patent number: 7524727
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 28, 2009
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Multigate device with recessed strain regions
    Patent number: 7525160
    Abstract: Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: April 28, 2009
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Justin K. Brask, Suman Datta, Brian S. Doyle, Robert S. Chau
  • DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE
    Publication number: 20090095984
    Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
    Type: Application
    Filed: December 18, 2008
    Publication date: April 16, 2009
    Inventors: Justin K. Brask, Suman Datta, Mark L. Doczy, James M. Blackwell, Matthew V. Metz, Jack T. Kavalieros, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7518196
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY
    Publication number: 20090090976
    Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
    Type: Application
    Filed: December 11, 2008
    Publication date: April 9, 2009
    Applicant: Intel Corporation
    Inventors: Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
    Publication number: 20090075445
    Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
    Type: Application
    Filed: November 19, 2008
    Publication date: March 19, 2009
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Brian S. Doyle, Robert S. Chau, Everett X. Wang, Philippe Matagne, Lucian Shifren, Been Y. Jin, Mark Stettler, Martin D. Giles
  • Metal gate device with reduced oxidation of a high-k gate dielectric
    Patent number: 7501336
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Matthew V. Mertz, Mark L. Doczy, Suman Datta, Robert S. Chau
  • Angled implantation for removal of thin film layers
    Publication number: 20090057788
    Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.
    Type: Application
    Filed: October 24, 2008
    Publication date: March 5, 2009
    Inventors: Michael L. Hattendorf, Justin K. Brask, Justin S. Sandford, Jack Kavalieros, Matthew V. Metz