Abstract: A dynamic power positioning method and a dynamic power positioning system thereof are disclosed. The method comprises the steps of: controlling a device to be measured to transmit a plurality of positioning signals with a plurality of transmission powers; making a plurality of known location devices to receive the plurality of positioning signals, and recording the intensities and the corresponding reception times of the plurality of positioning signals, and the coordinates of the plurality of known location devices to the database; finding out the known location device corresponding to a positioning signal having a higher signal intensity among the received plurality of positioning signals; obtaining a signal intensity-distance function and a signal intensity-distance standard deviation function from the database; and finding out the device location of the device to be measured according to the signal intensity-distance function and signal intensity-distance standard deviation function.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a P-type semiconductor layer is provided, where the P-type semiconductor layer includes a GaN-based material and an upper surface of the P-type semiconductor layer is a Ga surface. A first N-type semiconductor layer is formed on the P-type semiconductor layer, where the first N-type semiconductor layer comprises a GaN-based material. An upper surface of the first N-type semiconductor layer is an N surface. A part of the first N-type semiconductor layer is removed by wet etching to expose a part of the P-type semiconductor layer.

Abstract: A power management circuit and system thereof are provided. The power management circuit includes M×N computing units, a first power supply unit, a second power supply unit and N-1 connection interfaces. M and N are both natural numbers greater than 1. The first power supply unit supplies power to the computing units of the Nth row, the computing units of the Nth row supply power to the computing units of the (N-1)th row, respectively, and so on until the computing units of the 2nd row supply power to the computing units of the 1st row, respectively. The second power supply unit supplies power to the M×N computing units, and the N-1 connection interfaces coupled to corresponding computing units of the 1st column of the M×N computing units, respectively.

Abstract: Disclosed are a patterned substrate, a semiconductor device and a nanotube structure. The patterned substrate includes, in a vertical direction, a base plate and an AlN layer that are sequentially stacked. The patterned substrate includes, in the vertical direction, a first surface and a second surface that are oppositely arranged, a bottom surface of the base plate is the first surface of the patterned substrate, the second surface of the patterned substrate is a patterned surface, the second surface is provided with a plurality of grooves that are independent of each other in a horizontal direction and are arranged in an array, and at least part of the base plate is left below each of the plurality of grooves. According to the patterned substrate in the present application, a structure of the AlN layer is changed, so that an epitaxial structure grown subsequently is prevented from warping.

Abstract: The present invention provides a semiconductor structure and a preparation method thereof. A transition metal and an impurity are co-doped on a buffer layer above a substrate layer to reduce the leakage current of a semiconductor device, to improve the pinch-off behavior, and to avoid the device current collapse, moreover, the ranges of the concentration of the transition metal and the impurity in the buffer layer are controlled to ensure the balance of the leakage current during the dynamic characteristics of the device.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a channel layer and a barrier layer that are sequentially superimposed, and a gate region being defined on a surface of the barrier layer; and a p-type semiconductor material layer formed in the gate region, the p-type semiconductor material layer including at least one composition change element, and a component of the composition change element changing along an epitaxial direction.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a channel layer, a barrier layer located on the channel layer, a composition change layer located on the barrier layer, and a p-type semiconductor material layer located in the gate region of the composition change layer, wherein a gate region is defined on a surface of the composition change layer, and a material of the composition change layer includes at least one composition change element.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first P-type semiconductor layer is provided, and an N-type semiconductor layer and a second P-type semiconductor layer are formed in sequence on the first P-type semiconductor layer. The first P-type semiconductor layer, the N-type semiconductor layer and the second P-type semiconductor layer all include a GaN-based material. When the first P-type semiconductor layer is provided, its upper surface is controlled to be a Ga surface; when the N-type semiconductor layer is formed, its upper surface is controlled to be an N surface; when the second P-type semiconductor layer is formed, its upper surface is controlled to be an N surface.

Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and manufacturing methods for semiconductor structure and substrate thereof. In the method for manufacturing the substrate, at least one of groove is provided in each subunit region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two subunit regions, the at least one of groove is filled with heat conduction materials to form a substrate; in one of the at least one unit region, the at least two subunit regions respectively have different heat conduction coefficients.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer which are stacked. A buried layer made of AlGaN is disposed in the first n-type semiconductor layer. A trench at least penetrates through the second n-type semiconductor layer and the p-type semiconductor layer. At least part of the buried layer is reserved below the trench. A gate electrode is in the trench. The method is used to manufacture this semiconductor structure.

Abstract: The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming an amorphous layer on the substrate, wherein the amorphous layer includes a plurality of patterns to expose part of the substrate; forming a metal nitride layer on the amorphous layer; removing the amorphous layer to form a plurality of cavities between the substrate and the metal nitride layer; removing the substrate to form the semiconductor structure. In the present invention, an amorphous layer is formed on the substrate, and a metal nitride layer is formed on the amorphous layer. The amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the performance of the semiconductor structure, while the metal nitride layer can realize self-supporting.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.

Abstract: A method and system for programming a path-following robot to perform an operation along a continuous path while accounting for process equipment characteristics. The method eliminates the use of manual teaching cycles. In one example, a dispensing robot is programmed to apply a consistent bead of material, such as adhesive or sealant, along the continuous path. A computer-generated definition of the path, along with a model of dispensing equipment characteristics, are provided to an optimization routine. The optimization routine iteratively calculates robot tool center point path and velocity, and material flow, until an optimum solution is found. The optimized robot motion and dispensing equipment commands are then provided to an augmented reality (AR) system which allows a user to visualize and adjust the operation while viewing an AR simulation of dispensing system actions and a simulated material bead. Other examples include robotic welding or cutting along a continuous path.

Abstract: A preparation method for a resonant cavity light-emitting diode comprises: forming a first mirror and a first semiconductor layer on a substrate in sequence; forming an active layer on the first semiconductor layer; and forming a second semiconductor layer and a second mirror on the active layer in sequence. The preparation method further comprises: planarizing at least one of a first contact surface between the first semiconductor layer and the first mirror, and a second contact surface between the second semiconductor layer and the second mirror. Since the first contact surface between the first semiconductor layer and the first mirror, and/or the second contact surface between the second semiconductor layer and the second mirror is planarized, the light emission uniformity of the resonant cavity light-emitting diode can be improved.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate on which at least one light guide groove is provided, the light guide groove penetrating the substrate; and a light emitting structure disposed on one side of the substrate, the light emitting structure including at least one set of a first electrode and a second electrode. The light guide groove at least corresponds to one set of a first electrode and a second electrode to prevent bad points. A wavelength conversion dielectric layer is filled into the light guide groove to avoid a coffee ring effect and achieve uniform and full-color light emission of a light emitting device. The semiconductor structure may further save manufacturing costs and prevent crosstalk between light emitted from various light emitting units.

Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and a method for manufacturing the same. In the method for manufacturing the substrate, at least one of groove is provided in each unit sub-region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two unit sub-regions; in one of the at least one unit region, the at least two unit sub-regions respectively have different porosities, the premanufactured substrate is annealed to form a substrate, wherein openings of the grooves are healed to form self-healing layers, and the grooves that are not fully healed form gaps. When a susceptor transfers heat to the substrate, the unit sub-regions with different porosities respectively have different heat conduction efficiencies.

Abstract: An augmented reality (AR) system for diagnosis, troubleshooting and repair of industrial robots. The disclosed diagnosis guide system communicates with a controller of an industrial robot and collects data from the robot controller, including a trouble code identifying a problem with the robot. The system then identifies an appropriate diagnosis decision tree based on the collected data, and provides an interactive step-by-step troubleshooting guide to a user on an AR-capable mobile device, including augmented reality for depicting actions to be taken during testing and component replacement. The system includes data collector, tree generator and guide generator modules, and builds the decision tree and the diagnosis guide using a stored library of diagnosis trees, decisions and diagnosis steps, along with the associated AR data.

Abstract: Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type nitride semiconductor layer and an n-type nitride semiconductor layer formed on the substrate in sequence, the p-type nitride semiconductor layer having a first protruding structure at a gate region of the p-type nitride semiconductor layer; the n-type nitride semiconductor layer having a first through hole corresponding to the first protruding structure, exposing the gate region of the p-type nitride semiconductor layer; a channel layer conformally disposed on the n-type semiconductor layer and the first protruding structure; a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids impurities and defects brought to the channel layer and the barrier layer.

Abstract: Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type semiconductor layer, the p-type semiconductor layer being disposed on the substrate; an n-type semiconductor layer, the n-type semiconductor layer being disposed on the p-type semiconductor layer, a groove being formed in a gate region of the n-type semiconductor layer, and the first groove penetrating the n-type semiconductor layer; a channel layer, the channel layer being conformally disposed on the n-type semiconductor layer and in the first groove; and a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids bringing impurities and defects to the channel layer and the barrier layer.