Abstract: A laser device for optical communication comprises a first laser unit connected to a first optical fiber for supplying a transmission laser beam thereto. wherein the laser device is configured for providing a reference laser beam in addition to the transmission laser beam. For providing the reference laser beam the laser device further includes a second laser unit connected to a second optical fiber for supplying the reference laser beam to the second optical fiber. The first laser unit is configured for providing the transmission laser beam as a linear polarized beam that is polarized in a first polarization direction, and the second laser unit is configured for providing the reference laser beam as a linear polarized beam that is polarized in a second polarization direction.

Abstract: The present invention is a switching circuit driving method for power converters and its driving module. Such driving method and driving module can avoid the occurrence of valley jumping by replacing the original blanking time with a front blanking time or a back blanking time when a valley jumping occurs in the system, and avoid the noise problem caused by valley jumping.

Abstract: A method of manufacturing nitride semiconductor substrate, comprising: providing silicon-on-insulator substrate which comprises an underlying silicon layer, a buried silicon dioxide layer and a top silicon layer; forming a first nitride semiconductor layer on the top silicon layer; forming, in the first nitride semiconductor layer, a plurality of notches which expose the top silicon layer; removing the top silicon layer and forming a plurality of protrusions and a plurality of recesses on an upper surface of the buried silicon dioxide layer, wherein each of the plurality of protrusions is in contact with the first nitride semiconductor layer, and there is a gap between each of the plurality of recesses and the first nitride semiconductor layer; and epitaxially growing a second nitride semiconductor layer on the first nitride semiconductor layer, such that the first nitride semiconductor layer and the second nitride semiconductor layer form a nitride semiconductor substrate.

Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.

Abstract: A touch-and-display device operated with an active stylus is provided. A touch position is detected in a touch detection period. An uplink signal is transmitted and a downlink signal is detected in a stylus detection period. When the downlink signal is detected, it is determined if a distance between a stylus position and the touch position is less than or equal to a first predetermined distance. A stylus mode is not entered if the determination result is affirmative.

Abstract: Embodiments of the present application provide a semiconductor structure and a manufacturing method therefor. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. By decreasing a doping concentration of the transition metal in the second buffer layer, a tailing effect is avoided and current collapse is prevented. By doping periodically the impurity in the buffer layer, the impurity may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced. By using the periodic doping method, dislocations, caused by doping, in the buffer layer may be effectively reduced.

Abstract: The present application provides a semiconductor structure. The semiconductor structure includes a channel layer and a barrier layer provided on the channel layer. The barrier layer includes multiple barrier layers arranged in a stack, the multiple barrier sub-layers include at least three barrier sub-layers, and Al component proportions of the multiple barrier sub-layers vary along a growth direction of the barrier layer for at least one up-and-down fluctuation.

Abstract: A dynamic power positioning method and a dynamic power positioning system thereof are disclosed. The method comprises the steps of: controlling a device to be measured to transmit a plurality of positioning signals with a plurality of transmission powers; making a plurality of known location devices to receive the plurality of positioning signals, and recording the intensities and the corresponding reception times of the plurality of positioning signals, and the coordinates of the plurality of known location devices to the database; finding out the known location device corresponding to a positioning signal having a higher signal intensity among the received plurality of positioning signals; obtaining a signal intensity-distance function and a signal intensity-distance standard deviation function from the database; and finding out the device location of the device to be measured according to the signal intensity-distance function and signal intensity-distance standard deviation function.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a P-type semiconductor layer is provided, where the P-type semiconductor layer includes a GaN-based material and an upper surface of the P-type semiconductor layer is a Ga surface. A first N-type semiconductor layer is formed on the P-type semiconductor layer, where the first N-type semiconductor layer comprises a GaN-based material. An upper surface of the first N-type semiconductor layer is an N surface. A part of the first N-type semiconductor layer is removed by wet etching to expose a part of the P-type semiconductor layer.

Abstract: A power management circuit and system thereof are provided. The power management circuit includes M×N computing units, a first power supply unit, a second power supply unit and N-1 connection interfaces. M and N are both natural numbers greater than 1. The first power supply unit supplies power to the computing units of the Nth row, the computing units of the Nth row supply power to the computing units of the (N-1)th row, respectively, and so on until the computing units of the 2nd row supply power to the computing units of the 1st row, respectively. The second power supply unit supplies power to the M×N computing units, and the N-1 connection interfaces coupled to corresponding computing units of the 1st column of the M×N computing units, respectively.

Abstract: Disclosed are a patterned substrate, a semiconductor device and a nanotube structure. The patterned substrate includes, in a vertical direction, a base plate and an AlN layer that are sequentially stacked. The patterned substrate includes, in the vertical direction, a first surface and a second surface that are oppositely arranged, a bottom surface of the base plate is the first surface of the patterned substrate, the second surface of the patterned substrate is a patterned surface, the second surface is provided with a plurality of grooves that are independent of each other in a horizontal direction and are arranged in an array, and at least part of the base plate is left below each of the plurality of grooves. According to the patterned substrate in the present application, a structure of the AlN layer is changed, so that an epitaxial structure grown subsequently is prevented from warping.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a channel layer and a barrier layer that are sequentially superimposed, and a gate region being defined on a surface of the barrier layer; and a p-type semiconductor material layer formed in the gate region, the p-type semiconductor material layer including at least one composition change element, and a component of the composition change element changing along an epitaxial direction.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a channel layer, a barrier layer located on the channel layer, a composition change layer located on the barrier layer, and a p-type semiconductor material layer located in the gate region of the composition change layer, wherein a gate region is defined on a surface of the composition change layer, and a material of the composition change layer includes at least one composition change element.

Abstract: The present invention provides a semiconductor structure and a preparation method thereof. A transition metal and an impurity are co-doped on a buffer layer above a substrate layer to reduce the leakage current of a semiconductor device, to improve the pinch-off behavior, and to avoid the device current collapse, moreover, the ranges of the concentration of the transition metal and the impurity in the buffer layer are controlled to ensure the balance of the leakage current during the dynamic characteristics of the device.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first P-type semiconductor layer is provided, and an N-type semiconductor layer and a second P-type semiconductor layer are formed in sequence on the first P-type semiconductor layer. The first P-type semiconductor layer, the N-type semiconductor layer and the second P-type semiconductor layer all include a GaN-based material. When the first P-type semiconductor layer is provided, its upper surface is controlled to be a Ga surface; when the N-type semiconductor layer is formed, its upper surface is controlled to be an N surface; when the second P-type semiconductor layer is formed, its upper surface is controlled to be an N surface.

Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and manufacturing methods for semiconductor structure and substrate thereof. In the method for manufacturing the substrate, at least one of groove is provided in each subunit region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two subunit regions, the at least one of groove is filled with heat conduction materials to form a substrate; in one of the at least one unit region, the at least two subunit regions respectively have different heat conduction coefficients.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer which are stacked. A buried layer made of AlGaN is disposed in the first n-type semiconductor layer. A trench at least penetrates through the second n-type semiconductor layer and the p-type semiconductor layer. At least part of the buried layer is reserved below the trench. A gate electrode is in the trench. The method is used to manufacture this semiconductor structure.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.

Abstract: The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming an amorphous layer on the substrate, wherein the amorphous layer includes a plurality of patterns to expose part of the substrate; forming a metal nitride layer on the amorphous layer; removing the amorphous layer to form a plurality of cavities between the substrate and the metal nitride layer; removing the substrate to form the semiconductor structure. In the present invention, an amorphous layer is formed on the substrate, and a metal nitride layer is formed on the amorphous layer. The amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the performance of the semiconductor structure, while the metal nitride layer can realize self-supporting.