Patents by Inventor Kai FANG

Kai FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11946003
    Abstract: A system for producing needle coke and a method for producing needle coke using the system are provided. The system includes a coke tower, a pressure stabilization tower, a buffer tank and a coking fractionation tower. A pressure controller is provided at the top of the pressure stabilization tower for adjusting the pressure at the top thereof. An oil gas outlet of the coke tower is in communication with an oil gas inlet of the pressure stabilization tower through a pipeline. No pressure controller for adjusting the pressure at the top of the coke tower is provided in the coke tower or on the oil gas pipeline connecting the coke tower to the pressure stabilization tower.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: April 2, 2024
    Assignees: CHINA PETROLEUM & CHEMICAL CORPORATION, SINOPEC DALIAN RESEARCH INSTITUTE OF PETROLEUM AND PETROCHEMICALS.CO., LTD.
    Inventors: Dan Guo, Xiangchen Fang, Kai Qiao, Renqing Chu, Lianzhong Gou, Tianzuo Chen
  • Patent number: 11948939
    Abstract: An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Kai-Chi Wu, Ching-Hung Kao, Meng-I Kang, Kuo-Fang Ting
  • Patent number: 11943373
    Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 26, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Mao Cai Li, Zong You Wang, Kai Ban Zhou, Chang Qing Yang, Hu Lan, Li Kong, Jin Song Zhang, Yi Fang Shi, Geng Liang Zhu, Qu Cheng Liu, Qiu Ping Chen
  • Publication number: 20240088025
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20240087980
    Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Yen-Pin HSU, Li-Ling SU, Ming-Hsien LIN, Hsiao-Kang CHANG
  • Patent number: 11923357
    Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang Cheng, Kuang-Wei Yang, Cherng-Shiaw Tsai, Hsiaokang Chang
  • Patent number: 11920017
    Abstract: A method of a polyurethane foam includes the following steps of: (1) simultaneously pumping a mixed solution prepared from hydrogen peroxide, an organic acid, a catalyst and a stabilizer and a vegetable oil into a first microstructured reactor of a micro-channel modular reaction device for reacting to obtain a reaction solution containing epoxidized vegetable oil; (2) simultaneously pumping the reaction solution containing the epoxidized vegetable oil obtained from the step (1) and a compound of formula III into a second microstructured reactor of the micro-channel modular reaction device for reaction to obtain a vegetable oil polyol; and (3) reacting the vegetable oil polyol prepared from the step (2) with a foam stabilizer, a cyclohexylamine, an isocyanate and a foaming agent cyclopentane for foaming so as to prepare a rigid polyurethane foam.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: March 5, 2024
    Assignee: NANJING TECH UNIVERSITY
    Inventors: Kai Guo, Zheng Fang, Chengkou Liu, Ning Zhu, Jingjing Meng, Junjie Tao, Xin Hu, Xin Li, Chuanhong Qiu, Pingkai Ouyang
  • Patent number: 11915729
    Abstract: When writing data to a magnetic data storage medium, it is detected whether duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold. When the duration, before the transition, of the data to be written exceeds the predetermined threshold, the data is written by applying an initial pulse and then maintaining, until a shut-off pulse, a steady-state write current having an amplitude less than the initial pulse. A shut-off adjustment is determined based on a predetermined delay. The shut-off pulse is initiated at a time based on one bit period prior to the transition, adjusted by the shut-off adjustment. When the duration, before the transition, of the data to be written is at most equal to the predetermined threshold, the data is written by applying the initial pulse without applying a steady-state write current before the transition.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: February 27, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventors: Kai Wu, Hao Fang, Jorge Estuardo Licona
  • Patent number: 11912814
    Abstract: A preparation method of a flexible polyurethane foam includes the following steps of: (1) subjecting an epoxidized vegetable oil, a benzoylformic acid, a basic catalyst, and an inert solvent to a ring-opening reaction in a first microchannel reactor of a microchannel reaction device to obtain a vegetable oil polyol; (2) subjecting the vegetable oil polyol obtained in the step (1), a propylene oxide and an inert solvent to an addition polymerization reaction in a second microchannel reactor of the microchannel reaction device to obtain a vegetable oil polyol for flexible polyurethane foam; and (3) using the vegetable oil polyol for flexible polyurethane foam obtained in the step (2) as the unique polyol, and subjecting the same and an isocyanate polyol to a foaming reaction to obtain the flexible polyurethane foam.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 27, 2024
    Assignee: NANJING TECH UNIVERSITY
    Inventors: Kai Guo, Zheng Fang, Junjie Tao, Wei He, Chengkou Liu, Jindian Duan, Xin Li, Ning Zhu, Jiangkai Qiu, Shiyu Guo, Pingkai Ouyang
  • Publication number: 20240038528
    Abstract: A method for manufacturing a semiconductor structure includes: forming a dielectric layer on a base structure; forming a trench in the dielectric layer to expose the base structure; forming a metal contact in the trench; and performing a plurality of first atomic layer deposition (ALD) cycles to form a plurality of first atomic layers which cover the dielectric layer and the metal contact and which serve as an etch stop layer. Each of the first ALD cycles includes: forming a corresponding one of the first atomic layers; and performing a treatment to convert the corresponding first atomic layer into monocrystalline phase at a temperature not greater than 425° C.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Hsiao-Kang CHANG
  • Publication number: 20240038665
    Abstract: An interconnection structure is provided to include an interlayer dielectric (ILD) layer that is disposed over a substrate, a metal via that is disposed in the ILD layer, and a metal wire that is disposed over the metal via in the ILD layer and that is electrically connected to the metal via. The ILD layer includes silicon carbon nitride.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Hsiao-Kang CHANG
  • Publication number: 20240038586
    Abstract: A semiconductor structure includes a base structure, a plurality of electrically conductive features disposed on the base structure, and an isolation structure disposed on the base structure. The base structure includes a substrate. The electrically conductive features are spaced apart from each other. The isolation structure includes a first inter-metal dielectric feature extending horizontally to interconnect the electrically conductive features, a first air gap layer disposed in the isolation structure and around the electrically conductive features, and a first sustaining feature extending horizontally to interconnect the electrically conductive features and disposed between the first inter-metal dielectric feature and the first air gap layer. Methods for manufacturing the semiconductor structure are also disclosed.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Hsiao-Kang CHANG
  • Publication number: 20240038666
    Abstract: A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes a dielectric layer, an interconnect structure disposed in the dielectric layer, and an etch stop layer which is disposed on a lower end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of SixCyNz, wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cheng-Chin LEE, Yen-Ju WU, Hsin-Yen HUANG, Hsiao-Kang CHANG
  • Patent number: 11848198
    Abstract: A method for manufacturing a semiconductor device having a low-k carbon-containing dielectric layer includes: depositing a low-k carbon-containing dielectric material, which has a carbon content ranging from 16 atomic % to 23 atomic %, using a precursor mixture to form a carbon-containing dielectric layer having a k value ranging from 2.8 to 3.3 and a porosity ranging from 0.03% to 1.0%; forming the carbon-containing dielectric layer into a patterned carbon-containing dielectric layer having a recess therein by etching, the patterned carbon-containing dielectric layer having a porosity ranging from 1.0% to 2.0%; and filling the recess with an electrically conductive material to form an electrically conductive feature in the patterned carbon-containing dielectric layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang Cheng, Ting-Ya Lo, Hsiao-Kang Chang
  • Patent number: 11830808
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20230378168
    Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Kai-Fang CHENG, Kuang-Wei YANG, Cherng-Shiaw TSAI, Hsiaokang CHANG
  • Patent number: D1003340
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: October 31, 2023
    Inventor: Kai Fang
  • Patent number: D1003342
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 31, 2023
    Inventor: Kai Fang
  • Patent number: D1003983
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 7, 2023
    Inventor: Kai Fang
  • Patent number: D1016902
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: March 5, 2024
    Inventor: Kai Fang