Patents by Inventor Kai FANG

Kai FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12368738
    Abstract: A method for constructing a vehicle networking intrusion detection model based on federated learning is provided, which includes decoupling a local model according to a feature extractor and a classifier; selecting other vehicle clients with higher similarity to each vehicle client; collecting a local feature extractor from each vehicle client and distributing them to each vehicle client along with a global classifier obtained in a previous round, by a server; aggregating the local classifier and feature extractor from other vehicle clients to form an evaluation model; updating weights to obtain an updated local feature extractor, and combining it with the global classifier in the previous round to update the local model; aggregating feature representations extracted from a local dataset, and obtaining a current feature representation; collecting all current feature representations to train a global classifier and distributing them to vehicle clients that participate a next round of training.
    Type: Grant
    Filed: April 22, 2025
    Date of Patent: July 22, 2025
    Assignee: Zhejiang Agricultural and Forestry University
    Inventors: Kai Fang, Hailin Feng, Wei Wang, Ali Kashif Bashir, Tingting Wang
  • Publication number: 20250210571
    Abstract: A semiconductor device includes a first integrated circuit, a second integrated circuit and a bonding layer. The bonding layer is disposed between the first integrated circuit and the second integrated circuit, wherein the bonding layer includes a first layer and a second layer, the first layer is an aluminum nitride (AlN) layer, and the second layer is one of an aluminum oxide (AlO) layer and an aluminum oxynitride (AlON) layer.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fang Cheng, Hsiao-Kang Chang
  • Patent number: 12334431
    Abstract: A first dielectric layer is formed on a semiconductor structure. The first dielectric layer has a hardness higher than 10 GPa and a dielectric constant in a range between 1.0 and 4.0. A trench is formed in the first dielectric layer. A conductive feature is formed in the trench in contact with the semiconductor structure. A second dielectric layer is formed over the first dielectric layer and the conductive feature. A via structure is formed in the second dielectric layer in contact with the conductive feature.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang Cheng, Hsiao-Kang Chang
  • Publication number: 20250192670
    Abstract: An electronic component. The electronic component includes a base; a first semiconductor device attached to the base and having: a first Gallium nitride (GaN)-based switch having a first gate, a first source and a first drain, the first gate arranged to control a current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic component also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow; and a driver circuit coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches.
    Type: Application
    Filed: December 10, 2024
    Publication date: June 12, 2025
    Applicant: Navitas Semiconductor Limited
    Inventors: Chien-Chun HUANG, Milind GUPTA, Kai-Fang WEI, Xiucheng HUANG, Weijing DU, Renxiong ZHAN, Chih-Hsien HSIEH, Mingjie LI, Chi-Chih CHANG, Tao LIU, Songming ZHOU, Zhengdong ZHANG
  • Publication number: 20250140698
    Abstract: Contact structures and methods of forming the same are provided. A contact structure according to the present disclosure includes an etch stop layer (ESL), a first pillar feature and a second pillar feature disposed on the ESL, a metal feature disposed between the first pillar feature and the second pillar feature, the metal feature including a first sidewall, a bottom surface, a second sidewall, and a top surface, a dielectric liner extending continuously from a top surface of the first pillar feature, along the first sidewall, the bottom surface and the second sidewall of the metal feature, and onto a top surface of the second pillar feature, and a gap between the first pillar feature and a portion of the dielectric liner that extends along the first sidewall of the metal feature.
    Type: Application
    Filed: July 15, 2024
    Publication date: May 1, 2025
    Inventors: Kai-Fang Cheng, Hsiao-Kang Chang, Ming-Han Lee
  • Publication number: 20250118548
    Abstract: Semiconductor devices and methods of forming the same are provided. A method of the present disclosure includes depositing an aluminum nitride layer over a substrate, treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxynitride layer, depositing a III-V semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the III-V semiconductor layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 10, 2025
    Inventors: Kai-Fang Cheng, Hsiao-Kang Chang
  • Publication number: 20250112088
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chin LEE, Yen Ju WU, Shao-Kuan LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Jing Ting SU, Kai-Fang CHENG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
  • Publication number: 20250099319
    Abstract: Disclosed are a low-noise electromagnetic valve assembly, an air bag massage device, and a Control Method. The low-noise electromagnetic valve assembly includes an electromagnetic valve body, a flow guide piece, and a silencer; and the flow guide piece includes an air intake interface, an air release interface, an air bag interface, and a reserved interface The electromagnetic valve body enables the air bag interface to be in communication with the air intake interface or the air release interface, and the reserved interface is in communication with the air bag interface. The air release interface is in communication with the silencer, and the silencer is provided with a silencing air outlet. The low-noise electromagnetic valve assembly, the air bag massage device, and the control method can solve the problems of high production cost and poor usage experience of an electromagnetic valve.
    Type: Application
    Filed: September 29, 2022
    Publication date: March 27, 2025
    Inventors: Jiajun WU, Kai FANG, Wei WU
  • Patent number: 12223920
    Abstract: A backlight control circuit for a surface light emitting device is provided. The backlight control circuit includes a driving circuit. The driving circuit is configured to generate a plurality of driving currents to drive the surface light emitting device such that a plurality of backlight blocks of the surface light emitting device generate a plurality of brightness values. The surface light emitting device is divided into a first backlight area and a second backlight area. The second backlight area is closer to an edge of the surface light emitting device than the first backlight area. A first driving current of the plurality of driving currents is utilized for driving the light source of the first backlight area. A second driving current of the plurality of driving currents is utilized for driving the light source of the second backlight area. The second driving current is greater than the first driving current.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: February 11, 2025
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Li-Fei Wang, Yu-Lin Hsieh, Sheng-Kai Fang, Pei-Ling Kao
  • Publication number: 20250046673
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Patent number: 12205946
    Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang Cheng, Kuang-Wei Yang, Cherng-Shiaw Tsai, Hsiaokang Chang
  • Patent number: 12176247
    Abstract: A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, a metal containing layer disposed on the first conductive feature, and a second conductive feature disposed on and through the metal containing layer and in physical contact with the first conductive feature. The metal containing layer includes an M-O—X group, M representing a metal atom, O representing an oxygen atom, and X representing an element other than hydrogen.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
  • Publication number: 20240413010
    Abstract: A method of forming a semiconductor structure is provided. A first dielectric layer is formed over a substrate. A first metal pattern is formed through the first dielectric layer. A metal cap is formed over the first metal pattern. A surface portion of the metal cap is silicided to form a metal silicide pattern. A composite etch stop layer is formed on the first dielectric layer and the metal silicide pattern. A second dielectric layer is formed on the composite etch stop structure. A second metal pattern is formed through the second dielectric layer and the composite etch stop structure and landed on the metal silicide pattern.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen Ju Wu, Chi-Lin Teng, Cheng-Chin Lee, Shao-Kuan Lee, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang
  • Patent number: 12165945
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Publication number: 20240395700
    Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature disposed in the first dielectric layer, a second dielectric layer on the first dielectric layer, a conductive layer disposed in the second dielectric layer, and a liner layer disposed between the conductive layer and the second dielectric layer, wherein the liner layer has a portion extended over to a top surface of the second dielectric layer. The structure also includes a third dielectric layer on the second dielectric layer, a second conductive feature disposed in the third dielectric layer, wherein the second conductive feature has a portion in direct contact with the conductive layer. The structure further includes a first capping layer disposed between the second conductive feature and the third dielectric layer, and a portion of the first capping layer is extended to cover a top surface of the second conductive feature.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Kai-Fang CHENG, Hsiao-Kang CHANG
  • Patent number: 12154850
    Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, a conductive layer, a liner layer, a third dielectric layer, a second conductive feature, and a first capping layer. The first conductive feature is disposed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is in direct contact with the first dielectric layer. The conductive layer is disposed in the second dielectric layer. The liner layer is disposed between the conductive layer and the second dielectric layer. The third dielectric layer is formed on the second dielectric layer. The second conductive feature is disposed in the third dielectric layer. The first capping layer is disposed between the second conductive feature and the third dielectric layer.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang Cheng, Hsiao-Kang Chang
  • Publication number: 20240387250
    Abstract: A self-aligned interconnection structure includes a dielectric layer, a conductive feature, a capping layer, a first barrier layer and a second barrier layer. The conductive feature is formed in the dielectric layer, and the conductive feature has a top surface. The capping layer is disposed on the top surface of the conductive feature, and the capping layer does not cover the dielectric layer. The first barrier layer is disposed on the capping layer, and the first barrier layer does not cover the dielectric layer. The second barrier layer covers the first barrier layer and the dielectric layer, and the first barrier layer and the second barrier layer are formed of different materials.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fang CHENG, Hsiao-Kang CHANG
  • Publication number: 20240387364
    Abstract: An interconnection structure includes a first dielectric layer, a first conductive layer disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a second conductive layer disposed in the second dielectric layer in electrical contact with the first conductive layer, a third dielectric layer formed over the second dielectric layer, wherein the third dielectric layer comprises silicon carbon-nitride (SiCN) based material, and a resistor device disposed in the third dielectric layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ming-Hsien LIN, Hsiao-Kang CHANG
  • Publication number: 20240345079
    Abstract: The present invention provides a test device. The device includes a testing element and a house configured to accommodate the testing element, where the house is formed by folding a paper-made card, and the testing element is located in the housing. The housing is allowed to be in different change states to test or assay an analyte in a sample.
    Type: Application
    Filed: May 9, 2024
    Publication date: October 17, 2024
    Inventors: Guoliang YUAN, Jianqiu FANG, Siyu LEI, Kai FANG
  • Publication number: 20240332070
    Abstract: A method according to the present disclosure includes receiving a workpiece that includes a first conductive feature embedded in a first dielectric layer, selectively depositing a capping layer over the first conductive feature, depositing a first etch stop layer (ESL) over the capping layer, depositing a glue layer over the first ESL, depositing a second ESL over the glue layer, depositing a second dielectric layer over the second ESL, forming an opening through the second dielectric layer, the second ESL, the glue layer, and the first ESL to expose the capping layer, and forming a second conductive feature in the opening. A density of the second ESL is greater than a density of the first ESL.
    Type: Application
    Filed: July 10, 2023
    Publication date: October 3, 2024
    Inventors: Yen Ju Wu, Kai-Fang Cheng, Cheng-Chin Lee, Hsiao-Kang Chang, Hsin-Yen Huang