Abstract: A synchronous rectifier control apparatus includes a continuous conduction mode detection circuit configured to receive a voltage across a synchronous rectifier switch and determine whether the synchronous rectifier switch operates in a continuous conduction mode based on a rising slope of the voltage across the synchronous rectifier switch, a turn-off timer control circuit configured to measure a conduction time of the synchronous rectifier switch and turn off the synchronous rectifier switch after the conduction time of the synchronous rectifier switch in a current cycle is substantially equal to the conduction time measured in an immediately previous cycle, and a drive voltage control circuit configured to reduce a gate drive voltage of the synchronous rectifier switch after the conduction time of the synchronous rectifier switch in the current cycle is substantially equal to the conduction time measured in the immediately previous cycle multiplied by a predetermined percentage.

Abstract: A first dielectric layer is formed on a semiconductor structure. The first dielectric layer has a hardness higher than 10 GPa and a dielectric constant in a range between 1.0 and 4.0. A trench is formed in the first dielectric layer. A conductive feature is formed in the trench in contact with the semiconductor structure. A second dielectric layer is formed over the first dielectric layer and the conductive feature. A via structure is formed in the second dielectric layer in contact with the conductive feature.

Abstract: The present invention discloses a deformation controllable compression ring-based mechanical test system for rocks with variable stiffness and a test method thereof, which comprises a loading device, a variable stiffness regulating device, a data monitoring system and a controlling system; the energy storing spring in the loading device allows the rebounding direction of the loading device to be contrary to the strain direction of the test-piece, which eliminates the energy supplement of the loading device to the test-piece and realizes the loading of an oversized stiffness on the test system; the variable stiffness regulating device precisely regulates the loaded stiffness by regulating the loaded stiffness of the test system according to test requirements, which realizes the test of loading different stiffness on the same test system and avoids the influences of differences to loading parameters between different test systems on the test results.

Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, a conductive layer, a liner layer, a third dielectric layer, a second conductive feature, and a first capping layer. The first conductive feature is disposed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is in direct contact with the first dielectric layer. The conductive layer is disposed in the second dielectric layer. The liner layer is disposed between the conductive layer and the second dielectric layer. The third dielectric layer is formed on the second dielectric layer. The second conductive feature is disposed in the third dielectric layer. The first capping layer is disposed between the second conductive feature and the third dielectric layer.

Abstract: A control circuit is configured to control a flyback circuit comprising a primary-side switch, a secondary-side rectifier and a transformer. The control circuit comprises a feedback control circuit configured to generate a secondary-side control signal based on a current ripple signal of the transformer, and at least one of a direct-current component of an output voltage signal and a direct-current component of an output current signal of a secondary side of the flyback circuit, wherein the secondary-side control signal is configured to control a turn-off of the secondary-side rectifier, an isolated transmission circuit coupled to the feedback control circuit and configured to generate a first primary-side control signal based on the secondary-side control signal, and a primary control circuit coupled to the isolated transmission circuit and configured to control a turn-on of the primary-side switch in response to receiving the first primary-side control signal.

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

Abstract: The present invention discloses a deformation controllable compression ring-based mechanical test system for rocks with variable stiffness and a test method thereof, which comprises a loading device, a variable stiffness regulating device, a data monitoring system and a controlling system; the energy storing spring in the loading device allows the rebounding direction of the loading device to be contrary to the strain direction of the test-piece, which eliminates the energy supplement of the loading device to the test-piece and realizes the loading of an oversized stiffness on the test system; the variable stiffness regulating device precisely regulates the loaded stiffness by regulating the loaded stiffness of the test system according to test requirements, which realizes the test of loading different stiffness on the same test system and avoids the influences of differences to loading parameters between different test systems on the test results.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Abstract: A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, a metal containing layer disposed on the first conductive feature, and a second conductive feature disposed on and through the metal containing layer and in physical contact with the first conductive feature. The metal containing layer includes an M-O—X group, M representing a metal atom, O representing an oxygen atom, and X representing an element other than hydrogen.

Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Abstract: A method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line.

Abstract: A controller is for use in a power converter having a flyback transformer having a primary winding switched by a primary side transistor and a secondary winding switched by a secondary side transistor. The controller includes a line voltage detection circuit that activates a high line detect signal in response to detecting that an input line voltage is greater than a first threshold, a discontinuous conduction mode detection circuit activates a discontinuous conduction mode signal in response to detecting that the controller is operating in discontinuous conduction mode, and a switching controller coupled to the line voltage detection circuit and to the discontinuous conduction mode detection circuit that controls the primary side transistor and the secondary side transistor using partial zero voltage switching in response to an activation of the high line detect signal and the discontinuous conduction mode signal, and without using partial zero voltage switching otherwise.

Abstract: A wireless power transfer system has a signal source, an exciting coil, a pair of resonance coils having the same resonance frequency, a receiving coil and a load. The resonance frequency is regulated by the pair of resonance coils. The working frequency is made close to the resonance frequency of the resonance coils by means of the physical properties of a single-mode point in a non-Hermitian system, so as to regulate the energy transfer rate by controlling the distance between the receiving coil and the adjacent resonance coil. The system is located at the single-mode point while the coupling distance between the pair of resonance coils is changed and efficient wireless power transfer and mono-frequency efficient wireless power transfer within the kHz frequency range are realized by means of the physical properties of fixed frequency and minimum loss at the single-mode point.

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.