Patents by Inventor Kai FANG

Kai FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210119526
    Abstract: A controller is for use in a power converter having a flyback transformer having a primary winding switched by a primary side transistor and a secondary winding switched by a secondary side transistor. The controller includes a line voltage detection circuit that activates a high line detect signal in response to detecting that an input line voltage is greater than a first threshold, a discontinuous conduction mode detection circuit activates a discontinuous conduction mode signal in response to detecting that the controller is operating in discontinuous conduction mode, and a switching controller coupled to the line voltage detection circuit and to the discontinuous conduction mode detection circuit that controls the primary side transistor and the secondary side transistor using partial zero voltage switching in response to an activation of the high line detect signal and the discontinuous conduction mode signal, and without using partial zero voltage switching otherwise.
    Type: Application
    Filed: September 28, 2020
    Publication date: April 22, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: BongGeun CHUNG, Souhib HARB, Kai-Fang WEI
  • Patent number: 10983278
    Abstract: An apparatus comprises a substrate having a plateau region and a trench region, a metal layer over the plateau region, a semiconductor component over the trench region, wherein a gap is between the plateau region and the semiconductor component, an adhesion promoter layer over the plateau region, the semiconductor component and the gap, a dielectric layer over the adhesion promoter layer and a bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kai-Fang Cheng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10897206
    Abstract: A switched-mode power supply with near valley switching includes a quasi-resonant converter. The converter includes a switch element that is turned on not only at the valley, but also in a window range of ?tNVW close to the valley, where the voltage across the switch element is at its minimum. This advantageously reduces switching loss and maintains a balance between efficiency and frequency variation.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: January 19, 2021
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo Tao, Jung-Sheng Chen, Li Lin, Kai-Fang Wei, Chih-Hsien Hsieh, Hangseok Choi, Yue-Hong Tang
  • Patent number: 10867847
    Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Shao-Kuan Lee, Hai-Ching Chen
  • Publication number: 20200328152
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10779439
    Abstract: An apparatus for cooling an electronic component is provided. The apparatus includes a heat-absorbing base configured to contact the electronic component within a server device and a heat-dissipating body connected to the heat-absorbing base. The heat-dissipating body includes a heat-dissipating static feature and at least one heat-dissipating dynamic feature. The at least one heat-dissipating dynamic feature is configured to be repositioned about the heat-dissipating static feature to increase a surface area of the heat-dissipating body. Using hinge device and flexible metal conduit connect and transfer heat to them (dynamic and static feature). This apparatus will follow currently assembly process and also not impact the other device assembly method. The more space we have inside the product the more heat we can solve.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 15, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Yu-Nien Huang, Ching-Yu Chen, Erh-Kai Fang
  • Patent number: 10700000
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10662544
    Abstract: A surface treatment process for a metal article provides a uniform and unblemished surface finish to the metal article. The surface treatment process anodizes the metal article to form an anodic oxide layer on a surface, and the metal article is activated using a pre-dyeing solution. The pre-dyeing solution contains complex organic acid and sodium acetate. The anodic oxide layer of the metal article is dyed for color and the dyed anodic oxide layer of the metal article is finally sealed.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 26, 2020
    Assignees: HONGFUJIN PRECISION ELECTRONICS (CHENGDU) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Xiao-Gang Peng, Kai Fang, Yong-De Pei, Cheng-Bin Bai, Wei Liu, Qi Wang
  • Publication number: 20200133026
    Abstract: The device is directed to a reading glasses and goggles having lenses of different strengths and functions which can be replaced by users themselves, comprising single lens side ring, a bracket, a connecting rod, an upper eyeglass frame and a connecting block, and specifically having a second fixture slot in the top of said single lens side ring; a groove in the bottom of said upper eyeglass frame; the outer surface of the second fixture slot being engaged with the inner wall of the groove. The reading glasses and goggles having lenses of different strengths and functions can be replaced by users themselves, having lenses of different strengths and functions.
    Type: Application
    Filed: December 27, 2018
    Publication date: April 30, 2020
    Inventor: KAI FANG
  • Publication number: 20200058546
    Abstract: A method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line.
    Type: Application
    Filed: June 25, 2019
    Publication date: February 20, 2020
    Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
  • Patent number: 10521879
    Abstract: Methods, apparatuses, and computer program products for overlaying multisource media in VRAM are described. The primary media source is rendered in VRAM by an application program, and then the secondary media source(s) are rendered and blended to the primary source in VRAM at the same location of the primary source in VRAM, so no extra buffer is needed. This improves system performance and reduces power consumption, through reduced system bus, system memory, and CPU usage.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 31, 2019
    Assignee: Ubitus, Inc.
    Inventors: Chung-Chou Yeh, Yu-Ju Tseng, Kai-Fang Cheng
  • Patent number: 10523110
    Abstract: A synchronous rectifier (SR) controller includes a controller having an input adapted to be coupled to a drain of an SR transistor, and an output for providing a drive signal in response thereto, a gate driver having an input coupled to the output of the controller, and an output adapted to be coupled to a gate of the SR transistor for providing a gate signal thereto, a first transistor having a drain coupled to the gate terminal, a gate, and a source coupled to ground, and a protection circuit having an input coupled to the drain terminal, and an output coupled to the gate of the first transistor. The protection circuit is responsive to a voltage on the drain terminal exceeding a first voltage to provide a voltage on the gate of the first transistor greater than a turn-on voltage and less than an overvoltage of the first transistor.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: December 31, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zhibo Tao, Lei Chen, Kai-Fang Wei
  • Publication number: 20190364697
    Abstract: An apparatus for cooling an electronic component is provided. The apparatus includes a heat-absorbing base configured to contact the electronic component within a server device and a heat-dissipating body connected to the heat-absorbing base. The heat-dissipating body includes a heat-dissipating static feature and at least one heat-dissipating dynamic feature. The at least one heat-dissipating dynamic feature is configured to be repositioned about the heat-dissipating static feature to increase a surface area of the heat-dissipating body. Using hinge device and flexible metal conduit connect and transfer heat to them (dynamic and static feature). This apparatus will follow currently assembly process and also not impact the other device assembly method. The more space we have inside the product the more heat we can solve.
    Type: Application
    Filed: August 28, 2018
    Publication date: November 28, 2019
    Inventors: Chao-Jung CHEN, Yi-Nien HUANG, Ching-Yu CHEN, Erh-Kai FANG
  • Publication number: 20190285912
    Abstract: An eye protection lens includes a lens substrate, a blue light absorbing arrangement, and a lens enhancement arrangement. The blue light absorbing arrangement includes one or more blue light absorbing membranes provided on a surface of the lens substrate for blocking blue light penetrating through the lens substrate. The lens enhancement arrangement is sandwiched between the blue light absorbing arrangement and the lens substrate, wherein the lens enhancement arrangement includes one or more light diffusion membranes for enhancing a rigidity and light transmission of the lens substrate.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 19, 2019
    Applicant: Eyekeeper Global Inc.
    Inventor: Kai FANG
  • Publication number: 20190285786
    Abstract: A screen of an electronic tool includes a screen substrate and an eye protection arrangement including a plurality of blue light absorbing membranes and a plurality of light diffusion membranes alternating with the blue light absorbing membranes provided on a surface of the screen of the electronic tool. The blue light absorbing membranes are arranged for blocking blue light penetrating through the screen and the light diffusion membranes are arranged for enhancing a rigidity and light transmission of the screen.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 19, 2019
    Applicant: Eyekeeper Global Inc.
    Inventor: Kai Fang
  • Publication number: 20190259130
    Abstract: Methods, apparatuses, and computer program products for overlaying multisource media in VRAM are described. The primary media source is rendered in VRAM by an application program, and then the secondary media source(s) are rendered and blended to the primary source in VRAM at the same location of the primary source in VRAM, so no extra buffer is needed. This improves system performance and reduces power consumption, through reduced system bus, system memory, and CPU usage.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 22, 2019
    Applicant: Ubitus, Inc.
    Inventors: Chung-Chou Yeh, Yu-Ju Tseng, Kai-Fang Cheng
  • Patent number: 10332296
    Abstract: Methods, apparatuses, and computer program products for overlaying multisource media in VRAM are described.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 25, 2019
    Assignee: Ubitus Inc.
    Inventors: Chung-Chou Yeh, Yu-Ju Tseng, Kai-Fang Cheng
  • Publication number: 20190181765
    Abstract: A switched-mode power supply with near valley switching includes a quasi-resonant converter. The converter includes a switch element that is turned on not only at the valley, but also in a window range of ?tNVW close to the valley, where the voltage across the switch element is at its minimum. This advantageously reduces switching loss and maintains a balance between efficiency and frequency variation.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo TAO, Jung-Sheng CHEN, Li LIN, Kai-Fang WEI, Chih-HSIEN HSIEH, Hangseok CHOI, Yue-Hong TANG
  • Publication number: 20190161882
    Abstract: A surface treatment process for a metal article provides a uniform and unblemished surface finish to the metal article. The surface treatment process anodizes the metal article to form an anodic oxide layer on a surface, and the metal article is activated using a pre-dyeing solution. The pre-dyeing solution contains complex organic acid and sodium acetate. The anodic oxide layer of the metal article is dyed for color and the dyed anodic oxide layer of the metal article is finally sealed.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 30, 2019
    Inventors: XIAO-GANG PENG, KAI FANG, YONG-DE PEI, CHENG-BIN BAI, WEI LIU, QI WANG
  • Publication number: 20190131240
    Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao