Abstract: A method and system for constructing a lightweight container-based user environment (CUE), and a medium, the method including: preparing, by a main process, for communication, cloning a child process, and then becoming a parent process; elevating, by the child process, permission, executing namespace isolation, and cloning a grandchild process, and setting, by the parent process, cgroups for the grandchild process; and setting, by the grandchild process, permission of the grandchild process to execute a command and a file, preparing an overlay file system, setting a hostname, restricting permission, and executing an initialization script to start the container. Multiple users are allowed to customize their own environments, enabling the users to customize their environments more flexibly, achieving privacy isolation, and making it easier and more secure to update a system. Therefore, it is particularly applicable to a high-performance computing cluster.

Abstract: Various embodiments provide a fault diagnosis method and an apparatus. In those embodiments, a centralized management apparatus receives a first packet from a first network device by using a first IGP monitoring protocol session, where the first packet includes a first message sent by the first network device to a second network device. The centralized management apparatus receives a second packet from the second network device through a second IGP monitoring protocol session, where the second packet includes a second message sent by the second network device to the first network device. The centralized management apparatus performs fault diagnosis based on the first packet and the second packet.

Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a first board, a magnetic component, a second board and a power device. The first board includes a conductive component disposed between a first side and a second side opposite to each other. The magnetic component is disposed between the first side and the second side and includes a magnetic core and a winding. A first conductive terminal and a second conductive terminal are led out on the first side and the second side, respectively. The second board is disposed on the first board and includes a third side and a fourth side opposite to each other. The fourth side faces the first side. The power device is disposed on the third side of the second board and electrically connected to the first board.

Abstract: the present disclosure relates to an embedded packaging module comprising a first semiconductor device, a first packaging layer and a first wiring layer, the first semiconductor device having a first and a second face, at least two positioning bulges and at least one bonding pad being provided on the first face of the first semiconductor device; the first packaging layer being formed on both the first face and a surface adjacent to the first face, the positioning bulges being positioned in the first packaging layer, at least one first via hole being provided in the first packaging layer, the bottom of the first via hole being positioned in the bonding pad and contacting with the bonding pad; the first wiring layer being positioned on the side of the first packaging layer away from the first semiconductor device and being electrically connected with the bonding pad through the first via hole.

Abstract: The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; and a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit, wherein the bonding part is made from an insulated material with cohesiveness, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel, and wherein side surfaces of the two power chips are naked except the portions contacting the bonding part.

Abstract: The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.

Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a substrate, a power device, a leading component and a molding component. The substrate includes a first side, a second side and a conductive wire. The power device is disposed on the substrate and electrically connected with the conductive wire. The leading component is disposed on the substrate and includes a first horizontal portion and a vertical portion connected with each other. The vertical portion is electrically connected with the conductive wire. The leading component includes a first contact surface and a second contact surface, which are non-coplanar. The molding component is disposed on the substrate and covers at least portion of the substrate and at least portion of the leading component. The first contact surface and the second contact surface are uncovered by the molding component.

Abstract: The disclosure discloses a power module. The power module includes a substrate, a power chip, a bonding material, and at least one spacer. The substrate includes a circuit-patterned layer. The power chip bonded to the circuit-patterned layer by the bonding material. The spacer is located between the circuit-patterned layer and the power chip, so as to keep the power chip away from the circuit-patterned layer in a distance.

Abstract: A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.

Abstract: Methods for fabricating a thin film transistor and an array substrate, an array substrate and a display device are provided, and the fabrication method of a thin film transistor includes: forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area in a second thickness; etching the active layer film by using the first photoresist pattern as a mask to form an active layer; ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce a thickness of the photoresist area of the first thickness to form the second photoresist pattern. The second photoresist pattern is used as the mask to etch the source-drain electrode thin film.

Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a magnetic component, a bare power chip and a conductive set. The magnetic component includes a first surface and a second surface opposite to each other. The bare power chip is disposed on the magnetic component and includes a third surface and a fourth surface opposite to each other. The conductive set is disposed on the magnetic component and electrically connected with the magnetic component and the bare power chip. The third or fourth surface of the bare power chip is at least partially attached on the first or second surface of the magnetic component, and at least partially included in a projected envelopment of the corresponding first or second surface of the magnetic component, so as to facilitate the magnetic component to support the bare power chip.

Abstract: The present invention provides a power module including a substrate and a modular housing structure. The substrate includes an electronic element disposed thereon. The modular housing structure is disposed on the substrate and located around the electronic element. The modular housing structure includes a plurality of sidewalls configured to connect with each other detachably. Each sidewall includes two connecting elements disposed on two opposite ends thereof respectively. The two connecting elements of any one of the sidewalls are connected to two corresponding connecting elements of two adjacent sidewalls respectively. Consequently, the numbers and connections of the sidewalls are adjustable and varied according to the size of the substrate so as to avoid the waste of space and enhance the power density.

Abstract: A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.

Abstract: A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit board includes an insulating substrate and a conductive layer thereon. A bottom surface of the conductive layer touches a top surface of the insulating substrate. The insulating substrate has plural first openings to allow the conductive layer to be exposed from the bottom surface of the insulating substrate. The first electronic component is disposed on a top surface of the conductive layer. The second electronic component is disposed on the bottom surface of the insulating substrate and received in the first openings. The second electronic component is connected to the conductive layer via the first openings. At least one of the first electronic component and the second electronic component is a bare die.

Abstract: Methods for fabricating a thin film transistor and an array substrate, an array substrate and a display device are provided, and the fabrication method of a thin film transistor includes: forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area in a second thickness; etching the active layer film by using the first photoresist pattern as a mask to form an active layer; ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce a thickness of the photoresist area of the first thickness to form the second photoresist pattern. The second photoresist pattern is used as the mask to etch the source-drain electrode thin film.

Abstract: The present disclosure discloses a package module of a power conversion circuit and a manufacturing method thereof. The package module of the power conversion circuit is surface-mountable on a system board. The package module of the power conversion circuit includes: a substrate, a power device die, a molding layer and a plurality of pins. The substrate has a metal layer, an insulating substrate layer and a thermal conductive layer. The insulating substrate layer is disposed between the metal layer and the thermal conductive layer. The power device die is coupled to the metal layer. Devices on the metal layer of the substrate are embedded in the molding layer. The plurality of pins is electrically coupled to the metal layer and embedded in the molding layer, at least a contact surface of each of the pins which is electrically coupled to the system board is exposed, and the contact surface is parallel and/or perpendicular to the thermal conductive layer.

Abstract: The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased.

Abstract: The present invention provides a power module including a substrate and a modular housing structure. The substrate includes an electronic element disposed thereon. The modular housing structure is disposed on the substrate and located around the electronic element. The modular housing structure includes a plurality of sidewalls configured to connect with each other detachably. Each sidewall includes two connecting elements disposed on two opposite ends thereof respectively. The two connecting elements of any one of the sidewalls are connected to two corresponding connecting elements of two adjacent sidewalls respectively. Consequently, the numbers and connections of the sidewalls are adjustable and varied according to the size of the substrate so as to avoid the waste of space and enhance the power density.

Abstract: A method of fabricating a package module includes placing a pin frame having plural pins on a circuit substrate; bonding the pins to corresponding bonding areas on a circuit substrate, thereby connecting the pins to the bonding areas; cutting off a connecting portion of the pin frame; and bending the pins to be vertical to the circuit substrate. By placing the pins on the corresponding bonding areas on the circuit substrate through the pin frame, and then cutting off the connecting portion of the pin frame and bending the pins, the efficiency of assembling the package module can be greatly promoted.

Abstract: The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film transistor and a resin layer having at least one resin via hole, wherein a film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole. By providing the film-thickness-difference-adjusting layer, the film thickness difference at the resin via hole can be effectively reduced, and when a photolithographic process is performed, the difference of the thickness of the photoresist here and the thicknesses at other positions is reduced, so that the via hole fluctuation of a passivation layer caused by the larger film thickness difference at the resin via hole is improved, and the metal residue problem of the pixel electrodes is effectively avoided.