Patents by Inventor Kai Lu

Kai Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220021121
    Abstract: A dielectric resonator antenna and a dielectric resonator antenna array. The dielectric resonator antenna includes a ground plane, a dielectric resonator element operably coupled with the ground plane, and a feed network operably coupled with the dielectric resonator element for exciting the dielectric resonator antenna to provide a wideband omnidirectional response. The dielectric resonator element includes a plurality of portions, including, at least, an innermost portion and an outermost portion arranged around the innermost portion. The innermost portion has a first effective dielectric constant and outermost portion has a second, different effective dielectric constant.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Inventors: Kwok Wa Leung, Zhen-Xing Xia, Kai Lu
  • Publication number: 20210359958
    Abstract: This invention discloses a hierarchical switching fabric and deadlock avoidance method for ultra high radix network routers. The hierarchical switching fabric comprises a network-on-chip and K multi-port components. The multi-port component comprises a port module configured to receive packets by a high speed serializer/deserializer, code and format the packets, send the packets to a corresponding hyper packet module after coding and format conversion, and send the packets sent by the hyper packet module to the network; and the hyper packet module configured to perform protocol processing for the received data link level packets, discard illegal packets, forward legitimate packets to the network-on-chip, perform data error correcting, format conversion and channel mapping for the packets received from the network-on-chip, and send the packets to the corresponding port module.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 18, 2021
    Applicant: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Kai LU, Qiang WANG, Mingche LAI, Junsheng CHANG, Pingjing LU, Xingyun QI, Yi DAI, Fangxu LV, Jiaqing XU, Jijun CAO, Canwen XIAO, Lu LIU
  • Patent number: 11169908
    Abstract: A GUI testing device may be configured to execute a testing state machine for interacting with a software application to generate an initial screen of a GUI. The GUI testing device may be configured to determine a current state in the testing state machine based upon a matching trigger target in the initial screen to a given state. The current state may include an operation, and the operation may associate with a trigger target to operate on. The trigger may include a source state, a destination state, and a trigger target. The operation may include a user input operation, and an operation trigger target. The GUI testing device may be configured to perform the operation on the matching trigger target in the initial screen to generate a next screen of the GUI, and advance from the current state to a next state based upon the trigger.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 9, 2021
    Assignee: CITRIX SYSTEMS, INC.
    Inventor: Kai Lu
  • Patent number: 11075461
    Abstract: A horn antenna includes a waveguide portion and an antenna portion operably connected with the waveguide portion. The waveguide portion has a feed port. The antenna portion is arranged to receive a linearly polarized signal from the waveguide portion and to convert the received linearly polarized signal to a circularly polarized signal for transmission.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: City University of Hong Kong
    Inventors: Kwok Wa Leung, Kai Lu, Nan Yang
  • Publication number: 20210200285
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a substrate, a power device, a leading component and a molding component. The substrate includes a first side, a second side and a conductive wire. The power device is disposed on the substrate and electrically connected with the conductive wire. The leading component is disposed on the substrate and includes a first horizontal portion and a vertical portion connected with each other. The vertical portion is electrically connected with the conductive wire. The leading component includes a first contact surface and a second contact surface, which are non-coplanar. The molding component is disposed on the substrate and covers at least portion of the substrate and at least portion of the leading component. The first contact surface and the second contact surface are uncovered by the molding component.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 1, 2021
    Inventors: Shouyu Hong, Yiqing Ye, Kai Lu, Qingdong Chen, Le Liang, Jianhong Zeng
  • Publication number: 20210184360
    Abstract: A parallel-plate antenna or antenna array suitable for operation at millimeter wave frequencies. The antenna includes an antenna element having a ground plane with a slot and a pair of parallel plates connected to the ground plane. The parallel plates extend generally perpendicularly from the ground plane. In plan view, the slot is arranged between the parallel plates. The antenna also includes a feed operably coupled with the slot for feeding the slot during operation so as to generate a circularly polarized signal for radiation.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Kwok Wa Leung, Kai Lu
  • Publication number: 20210184359
    Abstract: A horn antenna includes a waveguide portion and an antenna portion operably connected with the waveguide portion. The waveguide portion has a feed port. The antenna portion is arranged to receive a linearly polarized signal from the waveguide portion and to convert the received linearly polarized signal to a circularly polarized signal for transmission.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Kwok Wa Leung, Kai Lu, Nan Yang
  • Patent number: 11036269
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a substrate, a power device, a leading component and a molding component. The substrate includes a first side, a second side and a conductive wire. The power device is disposed on the substrate and electrically connected with the conductive wire. The leading component is disposed on the substrate and includes a first horizontal portion and a vertical portion connected with each other. The vertical portion is electrically connected with the conductive wire. The leading component includes a first contact surface and a second contact surface, which are non-coplanar. The molding component is disposed on the substrate and covers at least portion of the substrate and at least portion of the leading component. The first contact surface and the second contact surface are uncovered by the molding component.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 15, 2021
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shouyu Hong, Yiqing Ye, Kai Lu, Qingdong Chen, Le Liang, Jianhong Zeng
  • Publication number: 20210143345
    Abstract: Embodiments of the present disclosure provide a flexible base material, a preparation method of the flexible base material, a flexible substrate and a preparation method of the flexible substrate. The flexible base material includes: a host flexible material; and carriers dispersed in the host flexible material and having magnetic particles adsorbed thereon, and the carriers have organophilic functional groups on their surface.
    Type: Application
    Filed: July 8, 2019
    Publication date: May 13, 2021
    Inventors: Yifeng QIN, Kai LU, Yongshan ZHOU, Dongsheng HUANG
  • Publication number: 20210033418
    Abstract: The invention discloses a plotting method for a three-dimensional time-space diagram showing a regional green-wave coordinated control effect. The plotting method includes the following steps: establishing a coordinate system of the three-dimensional time-space diagram; determining a specific position coordinate of each intersection in the coordinate system of the three-dimensional time-space diagram; generating a time prism of a signal timing plan of each intersection; determining a green-wave bandwidth of each arterial road; and generating a driving trajectory between the intersections, and making a green-wave band of each arterial road, and completing plotting.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 4, 2021
    Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Kai LU, Xin TIAN, Shuyan JIANG, Li WANG, Jianxun XU
  • Publication number: 20210011740
    Abstract: A method and system for constructing a lightweight container-based user environment (CUE), and a medium, the method including: preparing, by a main process, for communication, cloning a child process, and then becoming a parent process; elevating, by the child process, permission, executing namespace isolation, and cloning a grandchild process, and setting, by the parent process, cgroups for the grandchild process; and setting, by the grandchild process, permission of the grandchild process to execute a command and a file, preparing an overlay file system, setting a hostname, restricting permission, and executing an initialization script to start the container. Multiple users are allowed to customize their own environments, enabling the users to customize their environments more flexibly, achieving privacy isolation, and making it easier and more secure to update a system. Therefore, it is particularly applicable to a high-performance computing cluster.
    Type: Application
    Filed: July 12, 2020
    Publication date: January 14, 2021
    Applicant: National University of Defense Technology, People's Liberation Army of China
    Inventors: Kai LU, Wenzhe ZHANG, Ruibo WANG, Yinghui GAO, Wanqing CHI, Enqiang ZHOU, Min XIE, Yong DONG, Wei ZHANG, Jiaxin LI, Mingtian SHAO
  • Publication number: 20200403908
    Abstract: Various embodiments provide a fault diagnosis method and an apparatus. In those embodiments, a centralized management apparatus receives a first packet from a first network device by using a first IGP monitoring protocol session, where the first packet includes a first message sent by the first network device to a second network device. The centralized management apparatus receives a second packet from the second network device through a second IGP monitoring protocol session, where the second packet includes a second message sent by the second network device to the first network device. The centralized management apparatus performs fault diagnosis based on the first packet and the second packet.
    Type: Application
    Filed: September 7, 2020
    Publication date: December 24, 2020
    Inventors: Shunwan Zhuang, Zhenbin Li, Shiping Xu, Kai Lu
  • Publication number: 20200260586
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a first board, a magnetic component, a second board and a power device. The first board includes a conductive component disposed between a first side and a second side opposite to each other. The magnetic component is disposed between the first side and the second side and includes a magnetic core and a winding. A first conductive terminal and a second conductive terminal are led out on the first side and the second side, respectively. The second board is disposed on the first board and includes a third side and a fourth side opposite to each other. The fourth side faces the first side. The power device is disposed on the third side of the second board and electrically connected to the first board.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Shouyu Hong, Jinping Zhou, Min Zhou, Xiaoni Xin, Pengkai Ji, Kai Lu, Le Liang, Zhenqing Zhao
  • Publication number: 20200251438
    Abstract: the present disclosure relates to an embedded packaging module comprising a first semiconductor device, a first packaging layer and a first wiring layer, the first semiconductor device having a first and a second face, at least two positioning bulges and at least one bonding pad being provided on the first face of the first semiconductor device; the first packaging layer being formed on both the first face and a surface adjacent to the first face, the positioning bulges being positioned in the first packaging layer, at least one first via hole being provided in the first packaging layer, the bottom of the first via hole being positioned in the bonding pad and contacting with the bonding pad; the first wiring layer being positioned on the side of the first packaging layer away from the first semiconductor device and being electrically connected with the bonding pad through the first via hole.
    Type: Application
    Filed: December 30, 2019
    Publication date: August 6, 2020
    Applicant: Delta Electronics (Shanghai) CO., LTD
    Inventors: Zengsheng WANG, Xuetao GUO, Kai LU, Hui LI
  • Publication number: 20190287943
    Abstract: The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; and a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit, wherein the bonding part is made from an insulated material with cohesiveness, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel, and wherein side surfaces of the two power chips are naked except the portions contacting the bonding part.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Applicant: Delta Electronics (Shanghai) CO., LTD
    Inventors: Tao WANG, Zhenqing ZHAO, Kai LU, Zeng LI, Jianhong ZENG
  • Patent number: 10347533
    Abstract: The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: July 9, 2019
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Tao Wang, Zhenqing Zhao, Kai Lu, Zeng Li, Jianhong Zeng
  • Publication number: 20190138069
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a substrate, a power device, a leading component and a molding component. The substrate includes a first side, a second side and a conductive wire. The power device is disposed on the substrate and electrically connected with the conductive wire. The leading component is disposed on the substrate and includes a first horizontal portion and a vertical portion connected with each other. The vertical portion is electrically connected with the conductive wire. The leading component includes a first contact surface and a second contact surface, which are non-coplanar. The molding component is disposed on the substrate and covers at least portion of the substrate and at least portion of the leading component. The first contact surface and the second contact surface are uncovered by the molding component.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 9, 2019
    Inventors: Shouyu Hong, Yiqing Ye, Kai Lu, Qingdong Chen, Le Liang, Jianhong Zeng
  • Patent number: 10276522
    Abstract: The disclosure discloses a power module. The power module includes a substrate, a power chip, a bonding material, and at least one spacer. The substrate includes a circuit-patterned layer. The power chip bonded to the circuit-patterned layer by the bonding material. The spacer is located between the circuit-patterned layer and the power chip, so as to keep the power chip away from the circuit-patterned layer in a distance.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: April 30, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tao Wang, Zhen-Qing Zhao, Kai Lu, Zheng-Fen Wan, Hai-Bin Xu
  • Publication number: 20190043799
    Abstract: A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 7, 2019
    Inventors: Kai Lu, Zhenqing Zhao, Tao Wang
  • Patent number: 10192900
    Abstract: Methods for fabricating a thin film transistor and an array substrate, an array substrate and a display device are provided, and the fabrication method of a thin film transistor includes: forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area in a second thickness; etching the active layer film by using the first photoresist pattern as a mask to form an active layer; ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce a thickness of the photoresist area of the first thickness to form the second photoresist pattern. The second photoresist pattern is used as the mask to etch the source-drain electrode thin film.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 29, 2019
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Jiaxiang Zhang, Kai Lu