Patents by Inventor Kai Lu

Kai Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190013736
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a magnetic component, a bare power chip and a conductive set. The magnetic component includes a first surface and a second surface opposite to each other. The bare power chip is disposed on the magnetic component and includes a third surface and a fourth surface opposite to each other. The conductive set is disposed on the magnetic component and electrically connected with the magnetic component and the bare power chip. The third or fourth surface of the bare power chip is at least partially attached on the first or second surface of the magnetic component, and at least partially included in a projected envelopment of the corresponding first or second surface of the magnetic component, so as to facilitate the magnetic component to support the bare power chip.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Inventors: Shouyu Hong, Qingdong Chen, Kai Lu, Pengkai Ji, Xiaoni Xin, Min Zhou, Yu Zhang, Jianhong Zeng
  • Patent number: 10136545
    Abstract: The present invention provides a power module including a substrate and a modular housing structure. The substrate includes an electronic element disposed thereon. The modular housing structure is disposed on the substrate and located around the electronic element. The modular housing structure includes a plurality of sidewalls configured to connect with each other detachably. Each sidewall includes two connecting elements disposed on two opposite ends thereof respectively. The two connecting elements of any one of the sidewalls are connected to two corresponding connecting elements of two adjacent sidewalls respectively. Consequently, the numbers and connections of the sidewalls are adjustable and varied according to the size of the substrate so as to avoid the waste of space and enhance the power density.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: November 20, 2018
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tao Wang, Kai Lu, Zhenqing Zhao, Shouyu Hong, Wei Cheng
  • Patent number: 10128181
    Abstract: A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 13, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Kai Lu, Zhenqing Zhao, Tao Wang
  • Patent number: 10096562
    Abstract: A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit board includes an insulating substrate and a conductive layer thereon. A bottom surface of the conductive layer touches a top surface of the insulating substrate. The insulating substrate has plural first openings to allow the conductive layer to be exposed from the bottom surface of the insulating substrate. The first electronic component is disposed on a top surface of the conductive layer. The second electronic component is disposed on the bottom surface of the insulating substrate and received in the first openings. The second electronic component is connected to the conductive layer via the first openings. At least one of the first electronic component and the second electronic component is a bare die.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: October 9, 2018
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Le Liang, Kai Lu, Zhen-Qing Zhao, Zeng Li
  • Publication number: 20180166468
    Abstract: Methods for fabricating a thin film transistor and an array substrate, an array substrate and a display device are provided, and the fabrication method of a thin film transistor includes: forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area in a second thickness; etching the active layer film by using the first photoresist pattern as a mask to form an active layer; ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce a thickness of the photoresist area of the first thickness to form the second photoresist pattern. The second photoresist pattern is used as the mask to etch the source-drain electrode thin film.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 14, 2018
    Applicants: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Jiaxiang Zhang, Kai Lu
  • Patent number: 9892998
    Abstract: The present disclosure discloses a package module of a power conversion circuit and a manufacturing method thereof. The package module of the power conversion circuit is surface-mountable on a system board. The package module of the power conversion circuit includes: a substrate, a power device die, a molding layer and a plurality of pins. The substrate has a metal layer, an insulating substrate layer and a thermal conductive layer. The insulating substrate layer is disposed between the metal layer and the thermal conductive layer. The power device die is coupled to the metal layer. Devices on the metal layer of the substrate are embedded in the molding layer. The plurality of pins is electrically coupled to the metal layer and embedded in the molding layer, at least a contact surface of each of the pins which is electrically coupled to the system board is exposed, and the contact surface is parallel and/or perpendicular to the thermal conductive layer.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 13, 2018
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kai Lu, Zhenqing Zhao, Shouyu Hong, Tao Wang, Le Liang
  • Patent number: 9887183
    Abstract: The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: February 6, 2018
    Assignee: Delta Electronics, Inc.
    Inventors: Tao Wang, Zhenqing Zhao, Zeng Li, Kai Lu
  • Publication number: 20170339798
    Abstract: The present invention provides a power module including a substrate and a modular housing structure. The substrate includes an electronic element disposed thereon. The modular housing structure is disposed on the substrate and located around the electronic element. The modular housing structure includes a plurality of sidewalls configured to connect with each other detachably. Each sidewall includes two connecting elements disposed on two opposite ends thereof respectively. The two connecting elements of any one of the sidewalls are connected to two corresponding connecting elements of two adjacent sidewalls respectively. Consequently, the numbers and connections of the sidewalls are adjustable and varied according to the size of the substrate so as to avoid the waste of space and enhance the power density.
    Type: Application
    Filed: April 13, 2017
    Publication date: November 23, 2017
    Inventors: Tao Wang, Kai Lu, Zhenqing Zhao, Shouyu Hong, Wei Cheng
  • Patent number: 9806010
    Abstract: A method of fabricating a package module includes placing a pin frame having plural pins on a circuit substrate; bonding the pins to corresponding bonding areas on a circuit substrate, thereby connecting the pins to the bonding areas; cutting off a connecting portion of the pin frame; and bending the pins to be vertical to the circuit substrate. By placing the pins on the corresponding bonding areas on the circuit substrate through the pin frame, and then cutting off the connecting portion of the pin frame and bending the pins, the efficiency of assembling the package module can be greatly promoted.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: October 31, 2017
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Kai Lu, Zhen-Qing Zhao, Tao Wang
  • Patent number: 9799683
    Abstract: The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film transistor and a resin layer having at least one resin via hole, wherein a film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole. By providing the film-thickness-difference-adjusting layer, the film thickness difference at the resin via hole can be effectively reduced, and when a photolithographic process is performed, the difference of the thickness of the photoresist here and the thicknesses at other positions is reduced, so that the via hole fluctuation of a passivation layer caused by the larger film thickness difference at the resin via hole is improved, and the metal residue problem of the pixel electrodes is effectively avoided.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: October 24, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xuecheng Hou, Kai Lu, Jian Guo
  • Patent number: 9748205
    Abstract: A molding type power module includes: a leadframe including a first step and a second step; a first planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the first step respectively; and a second planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the second step respectively, wherein, the first surface of the first planar power device and the first surface of the second planar power device face each other, the projected areas thereof on a vertical direction at least partially overlap, and the first planar power device at least has one electrode electronically connected with the electrodes of the second planar power device.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 29, 2017
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kai Lu, Zhenqing Zhao, Tao Wang, Le Liang
  • Patent number: 9716117
    Abstract: The invention relates to the field of display technologies, and discloses a method for producing a via, a method for producing an array substrate, an array substrate and a display device to prevent a chamfer from being formed in producing the via, to promote the product quality and improve the display effect of the display device. The method for producing a via comprises: employing a first etching process to partially etch a top film layer in an area that needs to form a via above an electrode, wherein the vertical etching amount achieved by employing the first etching process is less than the thickness of the top film layer; and employing a second etching process for which the vertical etching rate is larger than the lateral etching rate to etch the remaining part in the area that needs to form a via, until the electrode is exposed.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 25, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Changjiang Yan, Kai Lu, Jian Guo, Zhenyu Xie
  • Patent number: 9679786
    Abstract: The disclosure discloses a packaging module of a power converting circuit and a method for manufacturing the same. The packaging module of the power converting circuit includes a substrate, a molding layer and a plurality of pins. A power device is assembled at the substrate, a plurality of pins electrically are coupled to the power device, the molding layer covers the surface of the substrate with the power device, and at least a contact surface of the pins configured to electrically connect an external circuit is exposed. The molding layer includes a main hat-body part and a hat-brim part, the main hat-body part and the hat-brim part form a hat-shaped molding layer, and the hat-brim part is used to increase a creepage distance between the contact surfaces of the pins located at the top of the molding layer and the bottom of the substrate.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: June 13, 2017
    Assignee: Delta Electronics, Inc.
    Inventors: Shouyu Hong, Kai Lu, Zhenqing Zhao
  • Patent number: 9653424
    Abstract: This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 16, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Xiaotian Zhang, Jun Lu, Kai Lu
  • Publication number: 20170133314
    Abstract: A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.
    Type: Application
    Filed: May 11, 2016
    Publication date: May 11, 2017
    Inventors: Kai Lu, Zhenqing Zhao, Tao Wang
  • Publication number: 20170062386
    Abstract: The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.
    Type: Application
    Filed: August 8, 2016
    Publication date: March 2, 2017
    Applicant: DELTA ELECTRONICS (SHANGHAI) CO., LTD
    Inventors: Tao WANG, Zhenqing ZHAO, Kai LU, Zeng LI, Jianhong ZENG
  • Publication number: 20170025379
    Abstract: A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit board includes an insulating substrate and a conductive layer thereon. A bottom surface of the conductive layer touches a top surface of the insulating substrate. The insulating substrate has plural first openings to allow the conductive layer to be exposed from the bottom surface of the insulating substrate. The first electronic component is disposed on a top surface of the conductive layer. The second electronic component is disposed on the bottom surface of the insulating substrate and received in the first openings. The second electronic component is connected to the conductive layer via the first openings. At least one of the first electronic component and the second electronic component is a bare die.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 26, 2017
    Inventors: Le LIANG, Kai LU, Zhen-Qing ZHAO, Zeng LI
  • Publication number: 20170012030
    Abstract: The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased.
    Type: Application
    Filed: May 11, 2016
    Publication date: January 12, 2017
    Applicant: DELTA ELECTRONICS,INC.
    Inventors: Tao WANG, Zhenqing ZHAO, Zeng LI, Kai LU
  • Publication number: 20160380005
    Abstract: The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film transistor and a resin layer having at least one resin via hole, wherein a film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole. By providing the film-thickness-difference-adjusting layer, the film thickness difference at the resin via hole can be effectively reduced, and when a photolithographic process is performed, the difference of the thickness of the photoresist here and the thicknesses at other positions is reduced, so that the via hole fluctuation of a passivation layer caused by the larger film thickness difference at the resin via hole is improved, and the metal residue problem of the pixel electrodes is effectively avoided.
    Type: Application
    Filed: April 14, 2016
    Publication date: December 29, 2016
    Inventors: Xuecheng HOU, Kai LU, Jian GUO
  • Publication number: 20160381785
    Abstract: A molding type power module includes: a leadframe including a first step and a second step; a first planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the first step respectively; and a second planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the second step respectively, wherein, the first surface of the first planar power device and the first surface of the second planar power device face each other, the projected areas thereof on a vertical direction at least partially overlap, and the first planar power device at least has one electrode electronically connected with the electrodes of the second planar power device.
    Type: Application
    Filed: March 25, 2016
    Publication date: December 29, 2016
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Kai LU, Zhenqing ZHAO, Tao WANG, Le LIANG