Patents by Inventor Kam-Tou SIO
Kam-Tou SIO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210166947Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
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Patent number: 11024579Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.Type: GrantFiled: April 12, 2019Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Yung-Sung Yen
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Publication number: 20210159120Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.Type: ApplicationFiled: February 5, 2021Publication date: May 27, 2021Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Ho Che Yu
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Publication number: 20210143150Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.Type: ApplicationFiled: September 29, 2020Publication date: May 13, 2021Inventors: WEI-LING CHANG, LEE-CHUNG LU, XIANGDONG CHEN, KAM-TOU SIO, SANG-CHI HUANG
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Publication number: 20210118793Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively. A length of the first conductive segment is greater than a length of the third conductive segment.Type: ApplicationFiled: December 23, 2020Publication date: April 22, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN
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Publication number: 20210118805Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kam-Tou SIO, Cheng-Chi CHUANG, Chia-Tien WU, Jiann-Tyng TZENG, Shih-Wei PENG, Wei-Cheng LIN
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Publication number: 20210118868Abstract: An integrated circuit structure includes a first well, a second well, a third well, a first set of implants and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion of the first well, extending in the first direction and having a second width. The second well has a second dopant type and is adjacent to the first well. The third well has the second dopant type, and is adjacent to the first well. The first portion of the first well is between the second well and the third well. The first set of implants is in the first portion of the first well, the second well and the third well. The second set of implants is in the second portion of the first well.Type: ApplicationFiled: December 23, 2020Publication date: April 22, 2021Inventors: Kam-Tou SIO, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Yi-Hsun CHIU
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Patent number: 10977421Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.Type: GrantFiled: February 18, 2020Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
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Patent number: 10978439Abstract: A method of generating a layout diagram includes: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.Type: GrantFiled: August 19, 2019Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kam-Tou Sio, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang, Ko-Bin Kao, Ru-Gun Liu, Shun Li Chen
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Patent number: 10971493Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; a fourth fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, a third portion, and a fourth portion of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure respectively. A first distance between the first fin structure and the second fin structure is different from a second distance between the third fin structure and the fourth fin structure.Type: GrantFiled: June 14, 2018Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kam-Tou Sio, Shang-Wei Fang, Jiann-Tyng Tzeng, Chew-Yuen Young
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Publication number: 20210082903Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.Type: ApplicationFiled: November 6, 2020Publication date: March 18, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
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Patent number: 10950456Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.Type: GrantFiled: October 14, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
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Publication number: 20210066182Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
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Patent number: 10937695Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.Type: GrantFiled: December 16, 2019Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Ho Che Yu
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Publication number: 20210028311Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.Type: ApplicationFiled: October 12, 2020Publication date: January 28, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
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Publication number: 20200411531Abstract: Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.Type: ApplicationFiled: May 14, 2020Publication date: December 31, 2020Inventors: Kam-Tou Sio, Yi-Hsun Chiu
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Patent number: 10879229Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.Type: GrantFiled: July 27, 2020Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
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Patent number: 10879120Abstract: A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.Type: GrantFiled: June 2, 2017Date of Patent: December 29, 2020Assignees: Taiwan Semiconductor Manufacturing, Company LimitedInventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou
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Patent number: 10879173Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively.Type: GrantFiled: January 31, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
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Patent number: 10867115Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.Type: GrantFiled: September 25, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Wei Peng, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio