Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.

Abstract: A method includes arranging a first cell having a first cell height in a first row. The method further includes arranging a second cell having a second cell height in a second row abutting the first row, wherein the second cell height is different from the first cell height. The method further includes placing a plurality of first cell pins within the first cell, wherein each of the plurality of first cell pins extends along a corresponding routing track. The method further includes placing a plurality of second cell pins over a plurality of selected via placement points in the second cell, wherein at least one second cell pin of the plurality of second cell pins extends along a second routing track across a boundary of the second cell and into the first cell.

Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(?90%)*T1)?Pmin?(Gmin+(?110%)*T1).

Abstract: An IC structure includes first and second cell rows extending in a first direction. The first cell row includes first cells each including one or more first fins having first source/drain regions of a first conductivity type and one or more second fins having second source/drain regions of a second conductivity type opposite the first conductivity type. The second cell row includes second cells each including one or more third fins having third source/drain regions of the first conductivity type and one or more fourth fins having fourth source/drain regions of the second conductivity type. The first cells have a same first number of the one or more first fins, and the second cells have a same second number of the one or more third fins less than the first number of the one or more first fins.

Abstract: A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.

Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

Abstract: A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via.

Abstract: An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.

Abstract: A method of generating a layout diagram for an integrated circuit. The method includes arranging a plurality of cells in the layout diagram. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.

Abstract: A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.

Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.

Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.