Patents by Inventor Kang Yeh

Kang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120110300
    Abstract: A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring logical units for mapping to the physical units of the data area and writing update data belonging to the logical pages of the logical units orderly into the physical pages of physical units gotten from the free area. The method further includes configuring root units for the logical pages, configuring an entry chain for each of the root units and building entries on the entry chains for recording update information of the updated logical pages, wherein each of the logical pages corresponds to a root unit. Accordingly, the table size for storing the update information is effectively reduced and the time for searching valid data is effectively shortened.
    Type: Application
    Filed: February 18, 2011
    Publication date: May 3, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20120110243
    Abstract: A data writing method for a rewritable non-volatile memory module is provided, the rewritable non-volatile memory module has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, a portion of the physical blocks are mapped to a plurality of logical blocks, and each of the logical blocks has a plurality of logical pages. The data writing method includes receiving data, and the data has a plurality of data bits and belongs to one of the logical pages. The data writing method also includes determining whether each of the data bits is a specific value. The data writing method further includes not writing the data into the physical pages when each of the data bits is the specific value. Thereby, the performance of a memory storage apparatus is improved.
    Type: Application
    Filed: January 25, 2011
    Publication date: May 3, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20120096321
    Abstract: A block management method for managing physical blocks of a rewritable non-volatile memory, and a memory controller and a memory storage apparatus using the same are provided. The method includes grouping the physical blocks into at least a data area, a free area, and a replacement area, and grouping the physical blocks of the data area and the free area into a plurality of physical units. The method also includes when one of the physical blocks belonging to of the physical units of the data area becomes a bad physical block, getting a physical block from the replacement area and replacing the bad physical block with the gotten physical block. The method further includes associating a physical unit that contains no valid data in the free area with the replacement area. Thereby, the physical blocks can be effectively managed and the access efficiency can be improved.
    Type: Application
    Filed: December 6, 2010
    Publication date: April 19, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 8131911
    Abstract: A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 6, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Jiunn-Yeong Yang, Chih-Kang Yeh
  • Patent number: 8117382
    Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: February 14, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
  • Publication number: 20120030411
    Abstract: A data protecting method for a portable memory storage apparatus is provided. The method includes determining whether a mode signal is at a data protecting mode, and performing a file hiding procedure to change a file allocation table if the mode signal is at the data protecting mode, wherein a host system coupled to the portable memory storage device is allowed to only access a portion of logical addresses of the portable memory storage apparatus according to the changed file allocation table and files stored in the portable memory storage apparatus before the file hiding procedure are written into another portion of the logical addresses. Additionally, the method still includes performing a file showing procedure to change the file allocation table if the mode signal is not at the data protecting mode, wherein the host system may access all the logical addresses according to the changed file allocation table.
    Type: Application
    Filed: September 15, 2010
    Publication date: February 2, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Ling Wang, Chih-Kang Yeh
  • Patent number: 8108589
    Abstract: A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: January 31, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu
  • Patent number: 8103820
    Abstract: A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: January 24, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu
  • Patent number: 8086787
    Abstract: A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number as a memory erased count, wherein the random number is smaller than the wear-leveling start value. The method also includes counting the memory erased count each time when the physical blocks are erased and determining whether the memory erased count is smaller than the wear-leveling start value, wherein a physical blocks switching is performed between the data area and the spare area when the memory erased count is not smaller then the wear-leveling start value. Accordingly, it is possible to uniformly use the physical blocks, so as to effectively prolong a lifetime of the store system.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: December 27, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Ruei-Cian Chen, Chih-Kang Yeh, Kian-Fui Seng
  • Publication number: 20110302364
    Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.
    Type: Application
    Filed: August 22, 2011
    Publication date: December 8, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
  • Patent number: 8074148
    Abstract: A memory management method and a controller for a non-volatile memory storage device are provided. The memory management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: December 6, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Hua Chu, Kuo-Yi Cheng, Chih-Kang Yeh
  • Patent number: 8074128
    Abstract: A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units and dividing the physical units as a usage area and a replacement area, wherein the physical blocks grouped into the same physical unit are accessed by using a multi-planes accessing command. The method also includes when one of the physical block of the physical unit in the usage area is damaged, replacing the physical unit having the damaged physical block with one physical unit selected from the replacement area and recording the undamaged physical block within the replaced physical unit if there is an applicable physical unit in the replacement area; and replacing the damaged physical block with one physical block selected from the replacement area if there is no applicable physical unit but an undamaged physical block in the replacement area.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: December 6, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Hua Chu, Chih-Kang Yeh, Horng-Sheng Yan
  • Patent number: 8065497
    Abstract: A data management method, a controller and a storage apparatus thereof are provided. The method is adapted for a storage apparatus having a plurality of blocks. Parts of the blocks are linked to configure a plurality of mother and child blocks (M&C block). The data management method includes: (a) checking whether a mother and child block currently to be written with data is the same of a mother and child block which has been most lately written with data; (b) when it is determined that the mother and child block currently to be written with data is not the same of the mother and child block which has been most lately written with data, saving a transient data of the mother and child block currently to be written with data to a mother and child block transient relationship table.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 22, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Hua Chu, Chih-Kang Yeh
  • Patent number: 8060686
    Abstract: A method, an apparatus and a controller for managing memories are provided. In the present invention, a data accessing format of each of the memories is adjusted such that the accessing units for each data accessing operation are unified. A mapping table is then established for recording the adjusted data accessing format. When a data accessing command is received from a host, the mapping table is inquired so as to execute the data accessing command. Accordingly, incompatibility of hardware structures can be resolved, and management of different types of flash memory can be achieved.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: November 15, 2011
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8054686
    Abstract: A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: November 8, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Chih-Jen Lee
  • Patent number: 8055873
    Abstract: A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: November 8, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Hua Chu, Chih-Kang Yeh, Jian-Yo Su, Jui-Hsien Chang
  • Patent number: 8055837
    Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: November 8, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
  • Patent number: 8046526
    Abstract: A wear leveling method for a non-volatile memory is provided. The non-volatile memory is substantially divided into a plurality of blocks, and these blocks are grouped into at least a data area, a spare area, a substitute area, and a temporary area. The wear leveling method includes selecting blocks from the spare area according to different purposes and executing a wear leveling procedure.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: October 25, 2011
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8037236
    Abstract: A flash memory writing method for writing data into a flash memory storage system is provided. In the present method, a big data usage number and a small data usage number are counted for each logical unit in the flash memory storage system, so as to respectively represent the numbers of writing a big data and a small data into each the logical unit. When a host system writes new data into a logical unit in the flash memory storage system, the new data is written through different writing processes according to the big data usage number and the small data usage number of the logical unit. Thereby, the data writing efficiency is improved and the lifespan of the flash memory storage system is prolonged.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: October 11, 2011
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8023255
    Abstract: A display device is provided. The display device is adapted for a notebook computer. The display device includes a display panel, a bezel, a back shell, and a reinforced glass plate. The bezel includes a receiving recess and an opening. The display panel is disposed in the receiving recess. The bezel exposes a part of the display panel from the opening. The back shell is assembled with the bezel. The back shell and the bezel cooperatively define an accommodating space. The display panel is accommodated in the accommodating space. The reinforced glass plate is assembled to the bezel for covering the part of the display panel exposed by the opening of the bezel.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: September 20, 2011
    Assignee: Compal Electronics, Inc.
    Inventors: Tzu-Hao Lu, Kang-Yeh Yu, His-Ming Cheng