Patents by Inventor Kang Yeh
Kang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100011153Abstract: A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages, and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages. The block management method includes configuring a plurality of logical blocks for being accessed by a host, recording the logical block belonged to a frequently accessed block and executing a special mode to use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of one logical block belonged to the frequently accessed block. Accordingly, it is possible to increase the access speed of a storage system.Type: ApplicationFiled: October 28, 2008Publication date: January 14, 2010Applicant: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Publication number: 20100011154Abstract: A data accessing method for a flash memory and a storage system and a controller using the same are provided. The data accessing method includes grouping a plurality of physical blocks of the flash memory into a data area, a spare area, and a random area and when a write command and a new data to be written are received from a host, determining whether the new data is a continuous data, wherein the new data is written temporarily into the physical blocks in the random area if the new data is not a continuous data. Thereby, the number of data moving and physical block erasing is reduced and accordingly the data accessing speed in a random writing mode is increased.Type: ApplicationFiled: November 25, 2008Publication date: January 14, 2010Applicant: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Publication number: 20100011151Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.Type: ApplicationFiled: September 15, 2008Publication date: January 14, 2010Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Hua Chu, Chih-Kang Yeh
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Publication number: 20090327585Abstract: A data management method a flash memory storage system and a controller using the same are provided. The data management method is used for accessing a flash memory of the flash memory storage system, wherein the flash memory includes a plurality of physical blocks and the physical blocks are grouped into a data area and a spare area. The data management method includes configuring a plurality of logical blocks for be accessed by a host. The data management method also includes dividing each physical block into a plurality of physical parts and mapping the logical blocks to the physical parts. The data management method further includes accessing the mapped physical parts according to the physical blocks to be accessed by the host. Accordingly, it is possible to increase the usage and the accessing speed of the physical blocks in the flash memory storage system.Type: ApplicationFiled: September 30, 2008Publication date: December 31, 2009Applicant: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Publication number: 20090307412Abstract: A memory management method for a non-volatile memory and a controller using the same are provided. The non-volatile memory is substantially divided into a plurality of blocks. First, non-erasing information of a plurality of memory units comprising at least one block is recoded and used as a reference to establish an evaluation value. Then, whether to move data of at least one block on the memory units to another memory unit according to the evaluation value is determined. Accordingly, problems of read disturb and data retention due to excessive reading times can be resolved.Type: ApplicationFiled: July 24, 2008Publication date: December 10, 2009Applicant: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Publication number: 20090300271Abstract: A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.Type: ApplicationFiled: August 25, 2008Publication date: December 3, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Jiunn-Yeong Yang, Chien-Hua Chu, Kuo-Yi Cheng, Li-Chun Liang, Chih-Kang Yeh
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Publication number: 20090287876Abstract: A method, an apparatus and a controller for managing memories are provided. In the present invention, a data accessing format of each of the memories is adjusted such that the accessing units for each data accessing operation are unified. A mapping table is then established for recording the adjusted data accessing format. When a data accessing command is received from a host, the mapping table is inquired so as to execute the data accessing command. Accordingly, incompatibility of hardware structures can be resolved, and management of different types of flash memory can be achieved.Type: ApplicationFiled: July 7, 2008Publication date: November 19, 2009Applicant: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Publication number: 20090287877Abstract: A multi non-volatile memory chip packaged storage system having a memory module, a controller, a first and a second control buses and a first and a second I/O buses is provided. The memory module at least includes a first and a second non-volatile memory chips which are both enabled by receiving a chip enabled signal via a chip enabled pin, wherein the memory module and the controller are stacked and packaged as a single chip. After the first and the second non-volatile memory chips are enabled by the chip enable signal via the chip enabled pin, the controller may active the first and second control buses and the first and second I/O buses to access the first and the second non-volatile memory chips, or only active the first control and I/O buses or the second control and I/O buses to access the corresponding first or second non-volatile memory chip.Type: ApplicationFiled: August 25, 2008Publication date: November 19, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Hua Chu, Kuo-Yi Cheng, Chih-Kang Yeh
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Publication number: 20090265505Abstract: A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system.Type: ApplicationFiled: June 27, 2008Publication date: October 22, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Jiunn-Yeong Yang, Chih-Kang Yeh
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Connection assembly for connecting bodies, and portable electronic apparatus and base using the same
Patent number: 7599178Abstract: A connection assembly, which is suitable to connect a first body of a portable electronic apparatus with a second body thereof, is provided. The connection assembly includes a positioning unit, first electrical connectors and a second electrical connector. The positioning unit is rotatably connected to the first body and removably connected to the second body. The first electrical connectors are connected to the positioning unit, and the second electrical connector is connected to the second body so as to connect to one of the first electrical connectors. Therefore, the connection assembly occupies only a little area of surfaces of the two bodies.Type: GrantFiled: March 27, 2007Date of Patent: October 6, 2009Assignee: Compal Electronics, Inc.Inventors: Wen-Yi Huang, Po-An Lin, Kang-Yeh Yu -
Publication number: 20090248961Abstract: A memory management method and a controller for a non-volatile memory storage device are provided. The memor management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page.Type: ApplicationFiled: August 6, 2008Publication date: October 1, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Hua Chu, Kuo-Yi Cheng, Chih-Kang Yeh
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Publication number: 20090217136Abstract: A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet.Type: ApplicationFiled: May 29, 2008Publication date: August 27, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Kuo-Yi Cheng, Chih-Kang Yeh
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Publication number: 20090198875Abstract: A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented.Type: ApplicationFiled: March 27, 2008Publication date: August 6, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Hua Chu, Chih-Kang Yeh, Jian-Yo Su, Jui-Hsien Chang
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Publication number: 20090175075Abstract: A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data.Type: ApplicationFiled: March 12, 2008Publication date: July 9, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Kang Yeh, Chih-Jen Lee
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Publication number: 20090172255Abstract: A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided.Type: ApplicationFiled: March 12, 2008Publication date: July 2, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Kang Yeh, Chien-Hua Chu
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Patent number: 7551426Abstract: A base suitable for a portable electronic apparatus is provided. The portable electronic apparatus includes a first body which has a first electrical connector. The base includes a second body, a supporting member, and a second electrical connector. The supporting member has a first end and a second end opposite to the first end. The first end is pivotally connected to the second body along a first rotation axis. The second electrical connector for connecting with the first electrical connector is pivotally connected to the second end along a second rotation axis. In addition, the second body has a recess for accommodating the supporting member and the second electrical connector after rotation. A portable electronic apparatus which has the base is also provided.Type: GrantFiled: March 30, 2007Date of Patent: June 23, 2009Assignee: Compal Electronics, Inc.Inventors: Wen-Yi Huang, Po-An Lin, Kang-Yeh Yu
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Publication number: 20090150597Abstract: A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block.Type: ApplicationFiled: March 20, 2008Publication date: June 11, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Jiunn-Yeong Yang, Jui-Hsien Chang, Chien-Hua Chu, Jian-Yo Su, Chih-Kang Yeh
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Publication number: 20090106484Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.Type: ApplicationFiled: February 4, 2008Publication date: April 23, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
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Publication number: 20090091978Abstract: A wear leveling method under limited system resources is provided, the wear levelling method is suitable for a non-volatile memory, the non-volatile memory is substantially divided into a plurality of blocks, and the blocks are at least grouped into a data area, a spare area and a substitution-transient area. The blocks within the data area may be divided into a plurality of lately-used blocks and a plurality of lately-unused blocks. The method includes only recording erase times of the lately-used blocks and blocks within the spare area and selecting a block used for the substitution-transient area is selected from the spare area according to a judgment condition of erase times of another block within the spare area plus a first threshold value. The method also includes performing a wear leveling procedure. Wherein, the selected block and the other block are selected in a random mode or a sequential mode.Type: ApplicationFiled: January 14, 2008Publication date: April 9, 2009Applicant: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Publication number: 20090094409Abstract: A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.Type: ApplicationFiled: January 22, 2008Publication date: April 9, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Kang Yeh, Chien-Hua Chu