Patents by Inventor Kang Yong Kim

Kang Yong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS
    Publication number: 20200381025
    Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.
    Type: Application
    Filed: May 15, 2020
    Publication date: December 3, 2020
    Applicant: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
    Patent number: 10825495
    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
    Patent number: 10811064
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Apparatuses and methods including memory commands for semiconductor memories
    Patent number: 10789186
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Dean Gans
  • Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
    Patent number: 10783940
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
    Patent number: 10748586
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • LOW-SPEED MEMORY OPERATION
    Publication number: 20200233592
    Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal. Such techniques may provide improved data bandwidth, improved command bandwidth, and/or reduced power consumption.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Inventor: Kang-Yong Kim
  • APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLE
    Publication number: 20200194044
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving, clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Kang-Yong Kim
  • SYSTEM-LEVEL TIMING BUDGET IMPROVEMENTS
    Publication number: 20200176038
    Abstract: Methods, systems, and devices for system-level timing budget improvements are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Inventor: Kang-Yong Kim
  • APPARATUSES AND METHODS FOR DETERMINING A PHASE RELATIONSHIP BETWEEN AN INPUT CLOCK SIGNAL AND A MULTIPHASE CLOCK SIGNAL
    Publication number: 20200143859
    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Low-speed memory operation
    Patent number: 10642512
    Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
    Patent number: 10600459
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • System-level timing budget improvements
    Patent number: 10593383
    Abstract: Methods, systems, and devices for system-level timing budget are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • SYSTEM-LEVEL TIMING BUDGET IMPROVEMENTS
    Publication number: 20200075069
    Abstract: Methods, systems, and devices for system-level timing budget improvements are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventor: Kang-Yong Kim
  • INTERCONNECTS FOR A MULTI-DIE PACKAGE
    Publication number: 20200075548
    Abstract: Systems, devices, and methods for interconnects for a multi-die package are described. A multi-die package may include a set of conductive pillars and two or more semiconductor dice that each include a bond pad. In some cases, the multi-die package may include a plurality of pillar-wire combinations, and a bond wire may couple a corresponding conductive pillar with a corresponding bond pad. Pillar-wire combinations may each collectively have a matched impedance, or pillar-wire combinations in different groups may have different collective impedances. In other cases, a conductive pillar may be directly coupled with a corresponding bond pad without a bond wire. Different pillar-wire combinations or directly-coupled pillars may carry different signals. In some cases, pillars may be individually impedance-matched to a desired impedance.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventors: Kang-Yong Kim, Chan Yoo, Dong Soon Lim, Jaekyu Song
  • LOW-SPEED MEMORY OPERATION
    Publication number: 20200073562
    Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal. Such techniques may provide improved data bandwidth, improved command bandwidth, and/or reduced power consumption.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventor: Kang-Yong Kim
  • APPARATUSES AND METHODS INCLUDING MEMORY COMMANDS FOR SEMICONDUCTOR MEMORIES
    Publication number: 20200050564
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kang-Yong Kim, Dean Gans
  • Apparatuses and methods for duty cycle error correction of clock signals
    Patent number: 10529398
    Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
    Patent number: 10515676
    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • APPARATUSES AND METHODS FOR DUTY CYCLE ERROR CORRECTION OF CLOCK SIGNALS
    Publication number: 20190385654
    Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim