Patents by Inventor Kang-Yoon Lee

Kang-Yoon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020136341
    Abstract: A phase-locked loop (PLL) frequency synthesizer incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider, two phase detectors each using a charge pump stage pumps. A fractional accumulator stage determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes.
    Type: Application
    Filed: August 29, 2001
    Publication date: September 26, 2002
    Applicant: GCT Semiconductor, Inc.
    Inventors: Hyungki Huh, Eunseok Song, Kang Yoon Lee, Yido Koo, Jeongwoo Lee, Joonbae Park
  • Publication number: 20020109182
    Abstract: An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.
    Type: Application
    Filed: October 26, 2001
    Publication date: August 15, 2002
    Inventors: Kang-yoon Lee, Jong-woo Park
  • Publication number: 20020094631
    Abstract: A method of forming a semiconductor device including a memory cell area having a plurality of memory cells and a peripheral circuit area for reading and writing data on the memory cells in the memory cell area of a semiconductor substrate is provided. Contact pads are formed on source/drain regions of transistors in the peripheral circuit area as well as in the memory cell area. The contact pads are concurrently formed on the source/drain regions of the transistors in the memory cell area and the peripheral circuit area. As a result, there is no step difference between the contact pads and, thus, it is easy to form metal contact plugs on the contact pads.
    Type: Application
    Filed: January 8, 2002
    Publication date: July 18, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Kang-Yoon Lee
  • Publication number: 20020070457
    Abstract: A metal contact structure of a semiconductor device and a method for forming the same are provided. The diameter of the upper portion of a contact hole that exposes a region of a lower conductive layer is formed to be larger than the diameter of the lower portion of the contact hole. The metal contact structure is formed without a void or a key hole. This is accomplished by forming at least two metal layers to fill the contact hole by performing a first deposition, an etch back, and a second deposition. The metal layer which fills the contact hole is etched back using a barrier metal layer formed on the entire surface of the contact hole as an etching stop layer. Thus, a void or key hole is not generated by making the upper portion of the contact hole to be wider than the lower portion of the contact hole and by depositing the metal which fills the contact hole through the processes of firstly depositing the metal, etching back the metal, and secondly depositing the metal.
    Type: Application
    Filed: November 8, 2001
    Publication date: June 13, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho-Won Sun, Kang-Yoon Lee, Jeong-Seok Kim, Dong-Won Shin, Tai-Heui Cho
  • Patent number: 6326270
    Abstract: Methods of forming integrated circuit memory devices may include steps to form memory cell access transistors therein. These steps may include steps to form a gate line on a semiconductor substrate and then implant dopants of first conductivity type into the semiconductor substrate to define a self-aligned impurity region therein. A spacer layer of a first material is then formed on a sidewall and upper surface of the gate line. An interlayer insulating layer of a second material is then formed on the spacer layer. A series of selective etching steps are then performed using different etchants. For example, a step is performed to selectively etch the interlayer insulating layer to define a contact hole therein, using the spacer layer as an etching mask to protect the gate line from etching damage. A selective etching step is then performed to convert the spacer layer into a sidewall spacer on the sidewall of the gate line.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: December 4, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Yoon Lee, Woo-Tag Kang, Jeong-Seok Kim, Yoo-Cheol Shin
  • Patent number: 6287971
    Abstract: A method for forming a cell capacitor in a DRAM device is provided. An interlayer insulating film is formed on a semiconductor substrate. The interlayer insulating film is patterned to form first buried contact holes for exposing a predetermined region of the semiconductor substrate. Plug patterns are filled in the first buried contact holes, and an etch stop film is formed on the entire surface of the resultant structure on which the plug patterns are formed. The etch stop film is patterned to form second buried contact holes having a smaller diameter than the top diameter of the plug patterns for exposing a predetermined region of the plug patterns. Storage electrodes for covering the second buried contact holes are formed on the resultant structure on which the second buried contact holes are formed.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: September 11, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-woo Park, Kang-yoon Lee
  • Patent number: 6207574
    Abstract: A dynamic random access memory (DRAM) cell storage node and a fabricating method thereof are provided. A storage contact plug 118 is formed in a first insulating layer 104 on a semiconductor substrate. A second insulating layer 110, a material layer 112, and a third insulating layer 114 are sequentially formed on the first insulating layer. The material layer prevents etchant of the third insulating layer from attacking the second insulating layer. The third insulating layer, the material layer, and the second insulating layer are sequentially etched to form an opening exposing the storage contact plug and a portion of the surface of the first insulating layer. The opening is filled with a conductive layer to form a storage node 116. The third insulating layer is etched until the top surface of the material layer is exposed, and the material layer is etched until the top surface of the second insulating layer is exposed.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: March 27, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-Yoon Lee
  • Patent number: 6162690
    Abstract: Methods of forming field effect transistors include the steps of forming an insulated gate electrode on a face of a substrate containing a semiconductor region therein extending to the face. A conductive layer of first conductivity type is also formed on the face and on a sidewall and upper surface of the insulated gate electrode. Dopants of first conductivity type are then diffused from the conductive layer into the semiconductor region to define source and drain regions of first conductivity type therein which are self-aligned to the insulated gate electrode. A step is also performed to remove a portion of the conductive layer to thereby define an intermediate source/drain contact (which is also self-aligned to the insulated gate electrode) and expose the upper surface of the insulated gate electrode. An electrode is then formed in contact with the intermediate source/drain contact.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: December 19, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-Yoon Lee
  • Patent number: 5900659
    Abstract: A buried bit line DRAM cell includes an active region having a protruding tap, formed in a semiconductor substrate. A device isolation region is formed in the substrate, outside the active region. A bit line laterally contacts the tap and is buried in the device isolation region. Accordingly, photolithography steps for forming a device isolation film twice and for forming a bit line contact can be omitted, thereby obtaining process simplicity and wider process margins.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: May 4, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-yoon Lee
  • Patent number: 5795801
    Abstract: A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: August 18, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-yoon Lee
  • Patent number: 5702969
    Abstract: A buried bit line DRAM cell includes an active region having a protruding tap, formed in a semiconductor substrate. A device isolation region is formed in the substrate, outside the active region. A bit line laterally contacts the tap and is buried in the device isolation region. Accordingly, photolithography steps for forming a device isolation film twice and for forming a bit line contact can be omitted, thereby obtaining process simplicity and wider process margins.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: December 30, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-yoon Lee