Patents by Inventor Kang-Yoon Lee

Kang-Yoon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7710835
    Abstract: A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-wook Kim, Choong-yul Cha, Jae-sup Lee, Kang-yoon Lee
  • Patent number: 7701002
    Abstract: A semiconductor device includes an isolation layer disposed in a semiconductor device to define an active region. A gate trench is disposed across the active region and extends to the isolation layer. An insulated gate electrode fills a portion of the gate trench and covers at least one sidewall of the active region. A portion of the gate electrode, that covers at least one sidewall of the active region, extends under a portion of the gate electrode that crosses the active region. An insulating pattern is disposed on the gate electrode.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Won Seo, Jae-Man Yoon, Kang-Yoon Lee, Young-Woong Son
  • Patent number: 7691719
    Abstract: Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: April 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-Ju Yun, Kang-Yoon Lee, In-Ho Nam
  • Patent number: 7619281
    Abstract: A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: November 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Young-Woong Son, Kang-Yoon Lee, Bong-Soo Kim
  • Patent number: 7586149
    Abstract: A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-man Yoon, Dong-gun Park, Kang-yoon Lee, Choong-ho Lee, Bong-soo Kim, Seong-goo Kim, Hyeoung-won Seo, Seung-bae Park
  • Publication number: 20090153259
    Abstract: A digitally controlled oscillator (DCO) includes a current generator which generates an electric current having a magnitude corresponding to an input signal, and a digitally controlled oscillating unit which generates an oscillating frequency based on an inductance which varies according to the magnitude of the electric current generated by the current generator.
    Type: Application
    Filed: April 17, 2008
    Publication date: June 18, 2009
    Inventors: Tae-wook KIM, Choong-yul CHA, Jae-sup LEE, Kang-yoon LEE
  • Patent number: 7521753
    Abstract: An integrated circuit device includes a substrate having a trench formed therein. An isolation layer is disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench. A buffer layer is disposed between the isolation layer and the trench. A gate insulating layer is disposed on the second sidewall portion of the trench and extends onto the substrate adjacent to the trench.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-yoon Lee, Jong-woo Park
  • Patent number: 7512390
    Abstract: An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: March 31, 2009
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kang Yoon Lee, Yido Koo, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
  • Publication number: 20090027088
    Abstract: A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.
    Type: Application
    Filed: November 6, 2007
    Publication date: January 29, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-wook KIM, Choong-yul CHA, Jae-sup LEE, Kang-yoon LEE
  • Patent number: 7439581
    Abstract: Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Goo Kim, Kang-Yoon Lee, Yun-Gi Kim, Bong-Soo Kim
  • Publication number: 20080211013
    Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.
    Type: Application
    Filed: May 9, 2008
    Publication date: September 4, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
  • Publication number: 20080179647
    Abstract: A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 31, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won Seo, Dong-hyun Kim, Kang-yoon Lee, Seong-goo Kim
  • Patent number: 7387931
    Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: June 17, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
  • Patent number: 7368352
    Abstract: In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 6, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-soo Kim, Jae-man Yoon, Seong-goo Kim, Hyeoung-won Seo, Dong-gun Park, Kang-yoon Lee
  • Publication number: 20080079070
    Abstract: A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.
    Type: Application
    Filed: May 1, 2007
    Publication date: April 3, 2008
    Inventors: Hyeoung-Won Seo, Young-Woong Son, Kang-Yoon Lee, Bong-Soo Kim
  • Patent number: 7352050
    Abstract: In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses, and a plurality of fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyuck-Jin Kang, Chang-Suk Hyun, Il-Young Moon, Kang-Yoon Lee, Kwang-bo Sim, Sang-Kil Jeon
  • Publication number: 20080061382
    Abstract: Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.
    Type: Application
    Filed: February 9, 2007
    Publication date: March 13, 2008
    Inventors: Seong-Goo Kim, Kang-Yoon Lee, Yun-Gi Kim, Bong-Soo Kim
  • Publication number: 20080003753
    Abstract: A semiconductor device includes an isolation layer disposed in a semiconductor device to define an active region. A gate trench is disposed across the active region and extends to the isolation layer. An insulated gate electrode fills a portion of the gate trench and covers at least one sidewall of the active region. A portion of the gate electrode, that covers at least one sidewall of the active region, extends under a portion of the gate electrode that crosses the active region. An insulating pattern is disposed on the gate electrode.
    Type: Application
    Filed: December 8, 2006
    Publication date: January 3, 2008
    Inventors: Hyeoung-Won Seo, Jae-Man Yoon, Kang-Yoon Lee, Young-Woong Son
  • Publication number: 20070284647
    Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.
    Type: Application
    Filed: February 12, 2007
    Publication date: December 13, 2007
    Inventors: Hyeoung-Won Seo, Jae-Man Yoon, Kang-Yoon Lee, Bong-Soo Kim
  • Publication number: 20070181925
    Abstract: A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 9, 2007
    Inventors: Jae-man Yoon, Bong-soo Kim, Hyeoung-won Seo, Kang-yoon Lee