Abstract: An active rectifier and a wireless power reception apparatus using the same are disclosed herein. The active rectifier includes first and fourth switches, second and third switches, and a synchronization control unit. The first and fourth switches are turned on while the voltage of an alternating current (AC) input is negative, and apply the current of the AC input to a rectifying capacitor. The second and third switches are turned on while a voltage of the AC input is positive, and apply the current of the AC input to the rectifying capacitor. The synchronization control unit compensates for the delay time of the comparator for detecting zero-crossing of the AC input so as to switch the first to fourth switches.

Abstract: A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

Abstract: A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

Abstract: A wireless power transmitter includes an amplifier configured to amplify a power; a transmitter configured to resonate the power amplified by the amplifier; and a reference signal provider configured to provide a reference signal to the amplifier and change a frequency of the reference signal.

Abstract: An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal.

Abstract: A synchronous rectifier includes: a rectifying circuit including transistors, the rectifying circuit being configured to generate rectified power by rectifying input power input to an input terminal of the rectifying circuit depending on switching operations of the transistors, and output the rectified power to an output terminal of the rectifying circuit; and a controller configured to apply a gate signal to each of the, and adjust a pulse width of the gate signal depending on a difference between the input power and the gate signal.

Abstract: A rectifier includes: a rectifying circuit configured to rectify alternating current (AC) power into direct current (DC) power through a switching operation; a driver configured to apply a switching signal to the rectifying circuit; and a signal modulator configured to select a parameter from among parameters of the switching signal based on a frequency of the switching signal, and adjust the selected parameter.

Abstract: A rectifier includes: first and second high side switches including source terminals connected to an alternating current input terminal and drain terminals connected to one end of an output capacitor; first and second low side switches including drain terminals connected to the alternating current input terminal and source terminals connected to a ground terminal and another end of the output capacitor; and a cross connector configured to allow parasitic capacitance of the first high side switch or the second high side switch to flow to a ground when the first high side switch or the second high side switch is turned off.

Abstract: An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal.

Abstract: A clock and data recovery circuit is disclosed herein. The clock and data recovery circuit includes a phase detection unit, a charge pump, a loop filter, a voltage control oscillator, and a frequency detection unit. The voltage control oscillator has oscillation frequency that is variable in response to a frequency adjustment signal, and outputs an oscillation signal. The frequency detection unit includes a reference clock divider, a counter, and an oscillation frequency control unit. The reference clock divider generates a count-enable signal based on a reference clock signal. The counter generates an oscillation count signal by counting the pulses of the oscillation signal of the voltage control oscillator or the pulses of divided signals resulting from dividing the oscillation signal while the count-enable signal is being enabled. The oscillation frequency control unit compares a target count value with the value of the oscillation count signal, and outputs the frequency adjustment signal.

Abstract: A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information.

Abstract: A synchronous direct current (DC)-DC buck converter and a method of controlling the waveforms of switching signals disclosed herein. The synchronous DC-DC buck converter generates a stepped-down output voltage using a first switch configured to apply an input voltage to an inductor and a second switch configured to switch in response to a second switching signal. The synchronous DC-DC buck converter includes a sawtooth generation unit, a driver oscillating signal generation unit, a switching signal generation unit, and a phase tracking unit. The sawtooth generation unit generates a sawtooth wave. The driver oscillating signal generation unit generates an error voltage between the output voltage and a reference voltage, and compares the sawtooth wave with the error voltage, so as to generate a driver oscillating signal. The switching signal generation unit generates each of the first and second switching signals. The phase tracking unit generates the frequency setting signal.

Abstract: An active rectifier and a wireless power reception apparatus using the same are disclosed herein. The active rectifier includes first and fourth switches, second and third switches, and a synchronization control unit. The first and fourth switches are turned on while the voltage of an alternating current (AC) input is negative, and apply the current of the AC input to a rectifying capacitor. The second and third switches are turned on while a voltage of the AC input is positive, and apply the current of the AC input to the rectifying capacitor. The synchronization control unit compensates for the delay time of the comparator for detecting zero-crossing of the AC input so as to switch the first to fourth switches.

Abstract: A synchronous direct current (DC)-DC buck converter and a method of controlling the waveforms of switching signals disclosed herein. The synchronous DC-DC buck converter generates a stepped-down output voltage using a first switch configured to apply an input voltage to an inductor and a second switch configured to switch in response to a second switching signal. The synchronous DC-DC buck converter includes a sawtooth generation unit, a driver oscillating signal generation unit, a switching signal generation unit, and a phase tracking unit. The sawtooth generation unit generates a sawtooth wave. The driver oscillating signal generation unit generates an error voltage between the output voltage and a reference voltage, and compares the sawtooth wave with the error voltage, so as to generate a driver oscillating signal. The switching signal generation unit generates each of the first and second switching signals. The phase tracking unit generates the frequency setting signal.

Abstract: A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information.

Abstract: There are provided a power supply device switching power input to a primary side to supply the power to a predetermined load connected to a secondary side electrically insulated from the primary side and a control circuit thereof. The control circuit generates a predetermined PWM signal to apply the PWM signal to a dimming switch connected to an end of the load and controls a switching frequency of the primary side, based on a control voltage generated according to a feedback signal according to the power supplied to the load and the PWM signal, and the control voltage maintains a constant difference between a minimum voltage level and a maximum voltage level regardless of a duty of the PWM signal.

Abstract: There are provided a power supply apparatus switching a power input to a primary side to supply the power to a predetermined load connected to a secondary side electrically insulated from the primary side and a control circuit thereof, the control circuit generating a predetermined PWM signal to apply the generated PWM signal to a dimming switch connected to an end of the load and controlling a switching frequency of the primary side based on a control voltage generated according to a feedback signal depending on the power supplied to the load and the PWM signal, wherein a voltage variation amount of the control voltage may be constantly maintained regardless of a duty of the PWM signal.

Abstract: There are provided a power supply device switching power input to a primary side to supply the power to a predetermined load connected to a secondary side electrically insulated from the primary side and a control circuit thereof. The control circuit generates a predetermined PWM signal to apply the PWM signal to a dimming switch connected to an end of the load and controls a switching frequency of the primary side, based on a control voltage generated according to a feedback signal according to the power supplied to the load and the PWM signal, and the control voltage maintains a constant difference between a minimum voltage level and a maximum voltage level regardless of a duty of the PWM signal.

Abstract: The present invention relates to an apparatus and a method for transmitting wireless power, and more particularly, to an apparatus and a method for transmitting wireless power that rapidly and precisely adjusts impedance so as to transmit desired power. Disclosed an apparatus for transmitting wireless power that performs wireless power transmission, including: an oscillator; an amplifier; an impedance matcher including a matching network which adjusts impedance according to a digital control signal and an analog signal, a sensor, a digital controller which outputs a digital control signal, and generates an analog control start signal when adjustment of the impedance by the digital control signal is completed, and an analog controller which outputs the analog control signal, and a transmitting antenna which radiates the magnetic field by using the transmission power.

Abstract: An output specification calibrating apparatus for a capacitive pressure sensor. The output specification calibrating apparatus enables adjustment of non-linearity, offset, and gain of the capacitive pressure sensor in a software manner at the time of shipment. Accordingly, it is feasible to easily adjust output specifications of the capacitive pressure sensor and to thereby meet various needs of customers.