Patents by Inventor Kang-Yoon Lee

Kang-Yoon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070181925
    Abstract: A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 9, 2007
    Inventors: Jae-man Yoon, Bong-soo Kim, Hyeoung-won Seo, Kang-yoon Lee
  • Publication number: 20070152255
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.
    Type: Application
    Filed: November 16, 2006
    Publication date: July 5, 2007
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20070120183
    Abstract: An integrated circuit device includes a substrate having a trench formed therein. An isolation layer is disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench. A buffer layer is disposed between the isolation layer and the trench. A gate insulating layer is disposed on the second sidewall portion of the trench and extends onto the substrate adjacent to the trench.
    Type: Application
    Filed: January 29, 2007
    Publication date: May 31, 2007
    Inventors: Kang-yoon Lee, Jong-woo Park
  • Publication number: 20070087499
    Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 19, 2007
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
  • Publication number: 20070082448
    Abstract: In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4 F2.
    Type: Application
    Filed: June 30, 2006
    Publication date: April 12, 2007
    Inventors: Bong-soo Kim, Jae-man Yoon, Seong-goo Kim, Hyeoung-won Seo, Dong-gun Park, Kang-yoon Lee
  • Publication number: 20070080385
    Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.
    Type: Application
    Filed: June 9, 2006
    Publication date: April 12, 2007
    Inventors: Bong-Soo Kim, Kang-Yoon Lee, Dong-Gun Park, Jae-Man Yoon, Seong-Goo Kim, Hyeoung-Won Seo
  • Publication number: 20070075359
    Abstract: In a circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device, the circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region; bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction; channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another; gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars; buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region; local interconnection lines contacting side surfaces of the gate
    Type: Application
    Filed: October 2, 2006
    Publication date: April 5, 2007
    Inventors: Jae-man Yoon, Dong-gun Park, Kang-yoon Lee, Choong-ho Lee, Bong-soo Kim, Seong-goo Kim, Hyeoung-won Seo, Seung-bae Park
  • Patent number: 7187032
    Abstract: An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: March 6, 2007
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kang-yoon Lee, Jong-woo Park
  • Publication number: 20070015362
    Abstract: Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 18, 2007
    Inventors: Cheol-Ju YUN, Kang-Yoon LEE, In-Ho NAM
  • Patent number: 7071535
    Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: July 4, 2006
    Assignee: GCT Semiconductor, Inc.
    Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonban Park, Kyeongho Lee
  • Patent number: 6963620
    Abstract: A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: November 8, 2005
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kang-Yoon Lee, Eunseok Song, Jeong Woo Lee, Joonbae Park, Kyeongho Lee
  • Publication number: 20050212081
    Abstract: In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses, and a plurality of fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 29, 2005
    Inventors: Hyuck-Jin Kang, Chang-Suk Hyun, Il-Young Moon, Kang-Yoon Lee, Kwang-bo Sim, Sang-Kil Jeon
  • Publication number: 20050045988
    Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 3, 2005
    Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
  • Publication number: 20040227208
    Abstract: An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.
    Type: Application
    Filed: June 14, 2004
    Publication date: November 18, 2004
    Inventors: Kang-yoon Lee, Jong-woo Park
  • Patent number: 6780707
    Abstract: A method of forming a semiconductor device including a memory cell area having a plurality of memory cells and a peripheral circuit area for reading and writing data on the memory cells in the memory cell area of a semiconductor substrate is provided. Contact pads are formed on source/drain regions of transistors in the peripheral circuit area as well as in the memory cell area. The contact pads are concurrently formed on the source/drain regions of the transistors in the memory cell area and the peripheral circuit area. As a result, there is no step difference between the contact pads and, thus, it is easy to form metal contact plugs on the contact pads.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: August 24, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-Yoon Lee
  • Patent number: 6767813
    Abstract: An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: July 27, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-yoon Lee, Jong-woo Park
  • Publication number: 20040086057
    Abstract: A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Applicant: GCT Semiconductor, Inc.
    Inventors: Kang-Yoon Lee, Eunseok Song, Jeong Woo Lee, Joonbae Park, Kyeongho Lee
  • Patent number: 6704383
    Abstract: A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: March 9, 2004
    Assignee: GCT Semiconductor, Inc.
    Inventors: Jeongwoo Lee, Yido Koo, Kang Yoon Lee, Eunseok Song, Hyungki Huh, Joonbae Park, Kyeongho Lee
  • Patent number: 6553089
    Abstract: A phase-locked loop (PLL) frequency synthesizer incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider, two phase detectors each using a charge pump stage pumps. A fractional accumulator stage determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: April 22, 2003
    Assignee: GCT Semiconductor, Inc.
    Inventors: Hyungki Huh, Eunseok Song, Kang Yoon Lee, Yido Koo, Jeongwoo Lee, Joonbae Park, Kyeongho Lee
  • Publication number: 20020136342
    Abstract: A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.
    Type: Application
    Filed: August 29, 2001
    Publication date: September 26, 2002
    Applicant: GCT Semiconductor, Inc.
    Inventors: Jeongwoo Lee, Yido Koo, Kang Yoon Lee, Eunseok Song, Hyungki Huh, Joonbae Park