Patents by Inventor Kang-Yoon Lee

Kang-Yoon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9413369
    Abstract: A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Joong Kim, Seok Ju Yun, Young Jun Hong, Hyung Gu Park, Kang Yoon Lee
  • Patent number: 9225248
    Abstract: A synchronous direct current (DC)-DC buck converter and a method of controlling the waveforms of switching signals disclosed herein. The synchronous DC-DC buck converter generates a stepped-down output voltage using a first switch configured to apply an input voltage to an inductor and a second switch configured to switch in response to a second switching signal. The synchronous DC-DC buck converter includes a sawtooth generation unit, a driver oscillating signal generation unit, a switching signal generation unit, and a phase tracking unit. The sawtooth generation unit generates a sawtooth wave. The driver oscillating signal generation unit generates an error voltage between the output voltage and a reference voltage, and compares the sawtooth wave with the error voltage, so as to generate a driver oscillating signal. The switching signal generation unit generates each of the first and second switching signals. The phase tracking unit generates the frequency setting signal.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: December 29, 2015
    Assignee: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Kang Yoon Lee, Hong Jin Kim, Young Jun Park, Jeong Ah Jang, Nak Young Ko, Dong Hyeon Seo
  • Publication number: 20150263625
    Abstract: A synchronous direct current (DC)-DC buck converter and a method of controlling the waveforms of switching signals disclosed herein. The synchronous DC-DC buck converter generates a stepped-down output voltage using a first switch configured to apply an input voltage to an inductor and a second switch configured to switch in response to a second switching signal. The synchronous DC-DC buck converter includes a sawtooth generation unit, a driver oscillating signal generation unit, a switching signal generation unit, and a phase tracking unit. The sawtooth generation unit generates a sawtooth wave. The driver oscillating signal generation unit generates an error voltage between the output voltage and a reference voltage, and compares the sawtooth wave with the error voltage, so as to generate a driver oscillating signal. The switching signal generation unit generates each of the first and second switching signals. The phase tracking unit generates the frequency setting signal.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 17, 2015
    Applicant: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Kang Yoon LEE, Hong Jin KIM, Young Jun PARK, Jeong Ah JANG, Nak Young KO, Dong Hyeon SEO
  • Publication number: 20150263534
    Abstract: An active rectifier and a wireless power reception apparatus using the same are disclosed herein. The active rectifier includes first and fourth switches, second and third switches, and a synchronization control unit. The first and fourth switches are turned on while the voltage of an alternating current (AC) input is negative, and apply the current of the AC input to a rectifying capacitor. The second and third switches are turned on while a voltage of the AC input is positive, and apply the current of the AC input to the rectifying capacitor. The synchronization control unit compensates for the delay time of the comparator for detecting zero-crossing of the AC input so as to switch the first to fourth switches.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 17, 2015
    Applicant: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Kang Yoon LEE, Jae Hyung JANG, Hyung Gu PARK, Joo Young CHUN
  • Publication number: 20150207514
    Abstract: A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 23, 2015
    Applicants: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Seong Joong KIM, Seok Ju YUN, Young Jun HONG, Hyung Gu PARK, Kang Yoon LEE
  • Patent number: 9066395
    Abstract: There are provided a power supply device switching power input to a primary side to supply the power to a predetermined load connected to a secondary side electrically insulated from the primary side and a control circuit thereof. The control circuit generates a predetermined PWM signal to apply the PWM signal to a dimming switch connected to an end of the load and controls a switching frequency of the primary side, based on a control voltage generated according to a feedback signal according to the power supplied to the load and the PWM signal, and the control voltage maintains a constant difference between a minimum voltage level and a maximum voltage level regardless of a duty of the PWM signal.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: June 23, 2015
    Assignees: SAMSUNG ELECTRO-MECHANICS CO., LTD., UNIVERSITY OF SEOUL INDUSTRY COOPERATION FOUNDATION
    Inventors: Dae Hoon Han, Seo Hyung Kim, Seung Ryung Ryu, Joong Ho Choi, Joo Hyung Lee, Hong Jin Kim, Jae Shin Lee, Kang Yoon Lee
  • Publication number: 20150002043
    Abstract: There are provided a power supply apparatus switching a power input to a primary side to supply the power to a predetermined load connected to a secondary side electrically insulated from the primary side and a control circuit thereof, the control circuit generating a predetermined PWM signal to apply the generated PWM signal to a dimming switch connected to an end of the load and controlling a switching frequency of the primary side based on a control voltage generated according to a feedback signal depending on the power supplied to the load and the PWM signal, wherein a voltage variation amount of the control voltage may be constantly maintained regardless of a duty of the PWM signal.
    Type: Application
    Filed: October 25, 2013
    Publication date: January 1, 2015
    Applicants: University of Seoul Industry Cooperation Foundation, SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hoon HAN, Seo Hyung KIM, Seung Ryung RYU, Joong Ho CHOI, Hong Jin KIM, Joo Hyung LEE, Jae Shin LEE, Kang Yoon LEE
  • Publication number: 20150002044
    Abstract: There are provided a power supply device switching power input to a primary side to supply the power to a predetermined load connected to a secondary side electrically insulated from the primary side and a control circuit thereof. The control circuit generates a predetermined PWM signal to apply the PWM signal to a dimming switch connected to an end of the load and controls a switching frequency of the primary side, based on a control voltage generated according to a feedback signal according to the power supplied to the load and the PWM signal, and the control voltage maintains a constant difference between a minimum voltage level and a maximum voltage level regardless of a duty of the PWM signal.
    Type: Application
    Filed: October 25, 2013
    Publication date: January 1, 2015
    Applicants: University of Seoul Industry Cooperation Foundation, SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hoon HAN, Seo Hyung KIM, Seung Ryung RYU, Joong Ho CHOI, Joo Hyung LEE, Hong Jin KIM, Jae Shin LEE, Kang Yoon LEE
  • Publication number: 20140319923
    Abstract: The present invention relates to an apparatus and a method for transmitting wireless power, and more particularly, to an apparatus and a method for transmitting wireless power that rapidly and precisely adjusts impedance so as to transmit desired power. Disclosed an apparatus for transmitting wireless power that performs wireless power transmission, including: an oscillator; an amplifier; an impedance matcher including a matching network which adjusts impedance according to a digital control signal and an analog signal, a sensor, a digital controller which outputs a digital control signal, and generates an analog control start signal when adjustment of the impedance by the digital control signal is completed, and an analog controller which outputs the analog control signal, and a transmitting antenna which radiates the magnetic field by using the transmission power.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 30, 2014
    Applicant: INTELLECTUAL DISCOVERY CO., LTD.
    Inventors: Kang Yoon LEE, Hyung Gu PARK, Jae Hyeong JANG, Ji Hun KANG
  • Publication number: 20140190237
    Abstract: An output specification calibrating apparatus for a capacitive pressure sensor. The output specification calibrating apparatus enables adjustment of non-linearity, offset, and gain of the capacitive pressure sensor in a software manner at the time of shipment. Accordingly, it is feasible to easily adjust output specifications of the capacitive pressure sensor and to thereby meet various needs of customers.
    Type: Application
    Filed: January 9, 2013
    Publication date: July 10, 2014
    Applicant: Auto Industrial Co., Ltd.
    Inventors: Kyong M. Park, Kang-Yoon LEE
  • Publication number: 20140035684
    Abstract: There are provided a control circuit for a digitally controlled oscillator and a control apparatus for a digitally controlled oscillator using the same. The control circuit for a digitally controlled oscillator includes: a peak detection circuit detecting amplitude of a signal output from the digitally controlled oscillator; and a transconductance control circuit comparing an output of the peak detection circuit with a predetermined reference signal to control a transconductance value of a negative transconductance circuit included in the digitally controlled oscillator.
    Type: Application
    Filed: November 13, 2012
    Publication date: February 6, 2014
    Applicants: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY, SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yoo Sam NA, Kang Yoon LEE, Dong Su LEE, Hyung Gu PARK, Hong Jin KIM, Gyu Suck KIM, Young Gun PU
  • Publication number: 20140009317
    Abstract: There are provided an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same. The analog-to-digital signal conversion method may include: generating a first digital output signal having N number of bits by comparing each of N number of delay signals detected from output terminals of N number of delay cells with a reference signal; generating a second digital output signal by comparing an auxiliary delay signal generated by an (N+1)th delay cell with the reference signal; and determining a change in a delay time of each of the N number of delay cells based on the first digital output signal and the second digital output signal.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 9, 2014
    Inventors: Yoo Sam NA, Kang Yoon Lee, Young Gun Pu, Hyung Gu Park, Hong Jin Kim, Yoo Hwan Kim, Dong Su Lee
  • Patent number: 8618972
    Abstract: There are provided an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same. The analog-to-digital signal conversion method may include: generating a first digital output signal having N number of bits by comparing each of N number of delay signals detected from output terminals of N number of delay cells with a reference signal; generating a second digital output signal by comparing an auxiliary delay signal generated by an (N+1)th delay cell with the reference signal; and determining a change in a delay time of each of the N number of delay cells based on the first digital output signal and the second digital output signal.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 31, 2013
    Assignees: Samsung Electro-Mechanics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Yoo Sam Na, Kang Yoon Lee, Young Gun Pu, Hyung Gu Park, Hong Jin Kim, Yoo Hwan Kim, Dong Su Lee
  • Patent number: 8604851
    Abstract: A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 10, 2013
    Assignees: Samsung Electronics Co., Ltd., Konkuk University Industrial Cooperation Corp
    Inventors: Kang-Yoon Lee, Young-Gun Pu, An-Soo Park, Joon-Sung Park, Jae-Sup Lee
  • Publication number: 20130316661
    Abstract: A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 28, 2013
    Applicants: Sungkyunkwan University Foundation for Corporate Collaboration, Samsung Electronics Co., Ltd.
    Inventors: Jaesup LEE, Hong Jin KIM, Hyung Gu PARK, Kang Yoon LEE
  • Patent number: 8552775
    Abstract: A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: October 8, 2013
    Assignees: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp.
    Inventors: Seung Sik Lee, Sangsung Choi, Young Ae Jeon, Sangjae Lee, Byoung Hak Kim, Mi Kyung Oh, Cheol-ho Shin, Kang-yoon Lee, YoungGun Pu, Joon-Sung Park
  • Patent number: 8482045
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20130147531
    Abstract: A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.
    Type: Application
    Filed: August 19, 2011
    Publication date: June 13, 2013
    Inventors: Kang-Yoon Lee, Young-Gun Pu, An-Soo Park, Joon-Sung Park, Jae-Sup Lee
  • Publication number: 20130043920
    Abstract: A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 21, 2013
    Applicants: Konkuk University Industrial Cooperation Corp., Electronics and Telecommunications Research Institute
    Inventors: Seung Sik LEE, Sangsung CHOI, Young Ae JEON, Sangjae LEE, Byoung Hak KIM, Mi Kyung OH, Cheol-ho SHIN, Kang-yoon LEE, YoungGun PU, Joon-Sung PARK
  • Patent number: 8330637
    Abstract: A Time-to-Digital Converter (TDC) is provided.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: December 11, 2012
    Assignees: Samsung Electronics Co., Ltd., Konkuk University Industry Cooperation Corp.
    Inventors: Jae-Sup Lee, Kang-Yoon Lee, An-Soo Park, Young-Gun Pu, Joon-Sung Park