Patents by Inventor Kaoru Yamamoto

Kaoru Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508557
    Abstract: A semiconductor manufacturing apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is configured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Joo An, Jeon-Il Lee, Kaoru Yamamoto, Jang-Hee Lee, Kee-Young Jun, Geun-O Jeong
  • Publication number: 20220316176
    Abstract: An excavator including a lower traveling body; an upper turning body turnably mounted to the lower traveling body; a hydraulic actuator configured to drive a driven part including the lower traveling body and the upper turning body; a hydraulic pump configured to supply hydraulic oil to the hydraulic actuator; a motor configured to drive the hydraulic pump; and a power storage device configured to supply power to the motor. The power storage device is mounted at a right front portion of the upper turning body. The hydraulic pump and the motor are mounted at a rear portion of the upper turning body.
    Type: Application
    Filed: March 16, 2022
    Publication date: October 6, 2022
    Inventors: Masaaki YAMAMOTO, Kaoru NAKADA
  • Patent number: 11432786
    Abstract: An X-ray fluoroscopic imaging apparatus includes first slide mechanism is disposed at a lower end of a support column, and a second slide mechanism is disposed at an upper end of the support column. When an operation unit has received an instruction, a controller performs a first mode in which the X-ray generator is moved in the predetermined direction by operating the second slide mechanism to move an X-ray support arm in the predetermined direction with respect to the upper end of the support column. Thereafter, the controller performs a second mode of operating the first slide mechanism to move the lower end of the support column at a predetermined first speed in the predetermined direction with respect to a support column support arm, while operating the second slide mechanism to move the X-ray support arm at a second speed smaller than the first speed in an opposite direction.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: September 6, 2022
    Assignee: FUJIFILM HEALTHCARE CORPORATION
    Inventor: Kaoru Yamamoto
  • Publication number: 20220238119
    Abstract: A neural network input unit 81 inputs a neural network in which a first network having a layer for inputting an anchor signal belonging to a predetermined class and a mixed signal including a target signal belonging to the class and a layer for outputting, as an estimation result, a reconstruction mask indicating a time-frequency domain in which the target signal is present in the mixed signal, and a second network having a layer for inputting the target signal extracted by applying the mixed signal to the reconstruction mask and a layer for outputting a result obtained by classifying the input target signal into a predetermined class are combined. A reconstruction mask estimation unit 82 applies the anchor signal and mixed signal to the first network to estimate the reconstruction mask of the class to which the anchor signal belongs.
    Type: Application
    Filed: May 28, 2019
    Publication date: July 28, 2022
    Applicant: NEC Corporation
    Inventors: Takafumi KOSHINAKA, Hitoshi YAMAMOTO, Kaoru KOIDA, Takayuki SUZUKI
  • Publication number: 20220199012
    Abstract: To make a frame size of a display device having an external compensation function smaller than those of the known display devices. Each of a plurality of unit circuits configuring a gate driver includes a first output control transistor including a second conduction terminal connected to a first output terminal connected to another unit circuit and a control terminal connected to a first internal node, a second output control transistor including a second conduction terminal connected to a second output terminal configured to output an on level signal for at least a part of a monitoring period and a control terminal connected to a second internal node, and an output circuit control transistor including a first conduction terminal connected to the first internal node and a second conduction terminal connected to the second internal node.
    Type: Application
    Filed: March 29, 2019
    Publication date: June 23, 2022
    Inventors: KAORU YAMAMOTO, RYO YONEBAYASHI
  • Publication number: 20220148509
    Abstract: With regard to a display device having an external compensation function, the occurrence of operational failure caused by off-leakage at a transistor is suppressed. A unit circuit configuring a gate driver is provided with a stabilization transistor including a control terminal, a first conduction terminal connected to a first internal node, and a second conduction terminal connected to a first control signal line, a stabilization circuit-configured to control a potential of the control terminal of the stabilization transistor-based on a potential of the first internal node, a first reset transistor including a control terminal, a first conduction terminal connected to a second output terminal, and a second conduction terminal connected to a first reference potential line, and a reset circuit configured to control a potential of the control terminal of the first reset transistor based on the potential of the first internal node.
    Type: Application
    Filed: May 14, 2019
    Publication date: May 12, 2022
    Inventor: KAORU YAMAMOTO
  • Patent number: 11314136
    Abstract: An active matrix substrate is provided with a demultiplexer circuit. Each unit circuit of the demultiplexer circuit splits the display signal from a single signal output line to n source bus lines. Each unit circuit includes n branch lines and n switching TFTs. The demultiplexer circuit includes boost circuits configured to boost the voltage applied to the gate electrodes of the switching TFTs. Each boost circuit includes a set section that pre-charges a node connected to the gate electrode, a boost section that boosts the potential of the node pre-charged by the set section, and a reset section that resets the potential of the node. The demultiplexer circuit includes an equalizer circuit configured to perform charge sharing by electrically connecting a first node boosted by the boost section of a first boost circuit and a second node boosted by the boost section of a second boost circuit.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 26, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Yamamoto
  • Publication number: 20220085025
    Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.
    Type: Application
    Filed: April 8, 2021
    Publication date: March 17, 2022
    Inventors: Hyunseok LIM, Minhyuk CHO, Kyung-Eun BYUN, Hyeonjin SHIN, Kaoru YAMAMOTO, Jungsoo YOON, Soyoung LEE, Geuno JEONG
  • Publication number: 20220071581
    Abstract: An X-ray fluoroscopic imaging apparatus includes first slide mechanism is disposed at a lower end of a support column, and a second slide mechanism is disposed at an upper end of the support column. When an operation unit has received an instruction, a controller performs a first mode in which the X-ray generator is moved in the predetermined direction by operating the second slide mechanism to move an X-ray support arm in the predetermined direction with respect to the upper end of the support column. Thereafter, the controller performs a second mode of operating the first slide mechanism to move the lower end of the support column at a predetermined first speed in the predetermined direction with respect to a support column support arm, while operating the second slide mechanism to move the X-ray support arm at a second speed smaller than the first speed in an opposite direction.
    Type: Application
    Filed: March 18, 2021
    Publication date: March 10, 2022
    Inventor: Kaoru YAMAMOTO
  • Patent number: 11270881
    Abstract: In a plasma deposition method, a substrate is loaded onto a substrate stage within a chamber. A first plasma is generated at a region separated from the substrate by a first distance. A first process gas is supplied to the first plasma region to perform a pre-treatment process on the substrate. A second plasma is generated at a region separated from the substrate by a second distance different from the first distance. A second process gas is supplied to the second plasma region to perform a deposition process on the substrate.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kaoru Yamamoto, Chang-Hyun Kim, Hyun-Jae Song, Keun-Wook Shin, Hyeon-Jin Shin, Sung-Joo An, Chang-Seok Lee, Kee-Young Jun, Geun-O Jeong, Jang-Hee Lee
  • Patent number: 11145268
    Abstract: An active matrix substrate according to an embodiment of the present invention includes: a plurality of source bus lines provided on a substrate; a source driver disposed in a peripheral region; signal output lines each connected to a corresponding one of output terminals of the source driver; and a demultiplexer circuit disposed in a peripheral region. The demultiplexer circuit includes unit circuits each configured to distribute a display signal from one signal output line to n source bus lines (n is an integer larger than or equal to 2). Each unit circuit includes n switching TFTs configured to perform individual on/off control of electrical connections of the n branch lines to the n source bus lines. The n branch lines being connected to one signal output lines. The demultiplexer circuit further includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the n switching TFTs.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: October 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Yamamoto
  • Publication number: 20210313169
    Abstract: Provided are apparatuses for manufacturing semiconductor devices. An apparatus includes a reaction chamber having a stage to be loaded on a substrate, wherein set plasma is formed over the stage, a plurality of gas supply lines connected to the reaction chamber, flow controllers formed on the plurality of gas supply lines, respectively, to control the amount of a gas supplied to the reaction chamber, and a gas splitter configured to supply a mixed gas to the flow controllers. The apparatus may be a thin film deposition apparatus using plasma and further include a flow control unit connected to the gas splitter and a gas supply source connected to the flow control unit.
    Type: Application
    Filed: March 22, 2021
    Publication date: October 7, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae SONG, Kaoru YAMAMOTO, Changhyun KIM, Shuji MORIYA, Jungsoo YOON, Soyoung LEE, Changseok LEE
  • Patent number: 11094538
    Abstract: Provided is a method of forming graphene. The method of forming graphene includes treating a surface of a substrate placed in a reaction chamber with plasma while applying a bias to the substrate, and growing graphene on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD).
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 17, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keunwook Shin, Changhyun Kim, Kaoru Yamamoto, Changseok Lee, Hyunjae Song, Eunkyu Lee, Kyung-Eun Byun, Hyeonjin Shin, Sungjoo An
  • Publication number: 20210196013
    Abstract: The jewelry member according to the present disclosure includes: a plurality of spherical bodies that are three-dimensionally arranged regularly and include an amorphous silicic acid; and a resin that is located in a gap among adjacent spherical bodies of the plurality of spherical bodies and includes a fluorescent dye.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 1, 2021
    Inventors: Hiroyuki HONGO, Kaoru YAMAMOTO
  • Publication number: 20210110781
    Abstract: An active matrix substrate according to an embodiment of the present invention includes: a plurality of source bus lines provided on a substrate; a source driver disposed in a peripheral region; signal output lines each connected to a corresponding one of output terminals of the source driver; and a demultiplexer circuit disposed in a peripheral region. The demultiplexer circuit includes unit circuits each configured to distribute a display signal from one signal output line to n source bus lines (n is an integer larger than or equal to 2). Each unit circuit includes n switching TFTs configured to perform individual on/off control of electrical connections of the n branch lines to the n source bus lines. The n branch lines being connected to one signal output lines. The demultiplexer circuit further includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the n switching TFTs.
    Type: Application
    Filed: April 5, 2018
    Publication date: April 15, 2021
    Inventor: Kaoru YAMAMOTO
  • Patent number: 10942409
    Abstract: Provided is an active matrix substrate (100) that includes multiple pixel TFTs (10), multiple gate wiring lines (GL) along which a scanning signal is supplied to the multiple pixel TFTs, multiple source wiring lines (SL) along which a display signal is supplied to the multiple pixel TFTs, a gate driver (20) that drives multiple gate wiring lines, and a source driver (30) that drives multiple source wiring lines. At least one of the gate driver and the source driver includes a current mirror circuit (70). The current mirror circuit is configured with two oxide semiconductor TFTs (71c and 72c) each of which includes an oxide semiconductor layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 9, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Yamamoto
  • Patent number: 10896656
    Abstract: An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region. Each unit circuit in the demultiplexer circuit includes n switching TFTs. The demultiplexer circuit includes a boost circuit capable of boosting a voltage applied to a gate electrode of the switching TFT. The boost circuit includes a set unit configured to perform a set action, a boost unit configured to perform a boost action, and a reset unit configured to perform a reset action. The set unit includes a setting TFT including a drain electrode connected to the drive signal line and a source electrode connected to a node connected to the gate electrode of the switching TFT. When the set unit performs the set action, a first signal voltage is supplied from the drive signal line to the drain electrode of the setting TFT, and a second signal voltage higher than the first signal voltage is supplied to the gate electrode of the setting TFT.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 19, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Yamamoto
  • Publication number: 20200409193
    Abstract: An active matrix substrate is provided with a demultiplexer circuit. Each unit circuit of the demultiplexer circuit splits the display signal from a single signal output line to n source bus lines. Each unit circuit includes n branch lines and n switching TFTs. The demultiplexer circuit includes boost circuits configured to boost the voltage applied to the gate electrodes of the switching TFTs. Each boost circuit includes a set section that pre-charges a node connected to the gate electrode, a boost section that boosts the potential of the node pre-charged by the set section, and a reset section that resets the potential of the node. The demultiplexer circuit includes an equalizer circuit configured to perform charge sharing by electrically connecting a first node boosted by the boost section of a first boost circuit and a second node boosted by the boost section of a second boost circuit.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 31, 2020
    Inventor: Kaoru YAMAMOTO
  • Publication number: 20200211489
    Abstract: The active matrix substrate includes a demultiplexer circuit disposed in a peripheral region. Unit circuits of the demultiplexer circuit each distribute a display signal from one signal output line to n source bus lines (n: two or greater). Each unit circuit includes n branch lines and n switching TFTs configured to perform individual on/off control of electrical connections of the branch lines to the source bus lines. The demultiplexer circuit includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the switching TFTs. Each boost circuit includes: a set-and-reset unit configured to perform set operation of pre-charging a node connected to the gate electrode and reset operation of resetting the potential of the node at different timings; and a boost unit configured to perform boost operation of boosting the potential of the node pre-charged by the set operation.
    Type: Application
    Filed: August 17, 2018
    Publication date: July 2, 2020
    Inventor: Kaoru YAMAMOTO
  • Patent number: 10679578
    Abstract: The display device includes drive circuits 301 provided in correspondence to the gate lines, respectively, and alternately switches a scanning period for scanning the gate lines and a non-scanning period during one vertical scanning period. The drive circuit 301 includes netA(n), an output switching element M5 connected to netA(n), and a reset circuit R. The output switching element M5 applies a selection voltage to the gate line GLn. The potential of netA(n) changes between a first potential that is equal to or higher than a threshold voltage of the output switching element M5, and a second potential that is lower than the first potential. In the drive circuit 301 wherein a period while netA(n) thereof has the second potential overlaps with the non-scanning period, the reset circuit R resets the potential of netA(n) to the second potential, before the resumption of the scanning period after the non-scanning period.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 9, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kohhei Tanaka, Kaoru Yamamoto, Tokihiro Yokono