Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

Abstract: A display device that includes pixel circuits, in each of which a plurality of types of transistors coexist, and that operates normally is implemented while suppressing an increase in processing cost. Each unit circuit includes a first control circuit (311), a first output circuit (321), and a second output circuit (322). The first output circuit (321) includes a first output terminal (38) connected to a first scanning signal line; a P-type transistor (M4) having a control terminal connected to a first internal node (N1), a first conductive terminal to which a gate high potential (VGH) is provided, and a second conductive terminal connected to the first output terminal (38); and a N-type transistor (M5) having a control terminal connected to the first internal node (N1), a first conductive terminal connected to the first output terminal (38), and a second conductive terminal to which a gate low potential (VGL) is provided.

Abstract: A semiconductor manufacturing apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is configured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.

Abstract: An X-ray fluoroscopic imaging apparatus includes first slide mechanism is disposed at a lower end of a support column, and a second slide mechanism is disposed at an upper end of the support column. When an operation unit has received an instruction, a controller performs a first mode in which the X-ray generator is moved in the predetermined direction by operating the second slide mechanism to move an X-ray support arm in the predetermined direction with respect to the upper end of the support column. Thereafter, the controller performs a second mode of operating the first slide mechanism to move the lower end of the support column at a predetermined first speed in the predetermined direction with respect to a support column support arm, while operating the second slide mechanism to move the X-ray support arm at a second speed smaller than the first speed in an opposite direction.

Abstract: To make a frame size of a display device having an external compensation function smaller than those of the known display devices. Each of a plurality of unit circuits configuring a gate driver includes a first output control transistor including a second conduction terminal connected to a first output terminal connected to another unit circuit and a control terminal connected to a first internal node, a second output control transistor including a second conduction terminal connected to a second output terminal configured to output an on level signal for at least a part of a monitoring period and a control terminal connected to a second internal node, and an output circuit control transistor including a first conduction terminal connected to the first internal node and a second conduction terminal connected to the second internal node.

Abstract: With regard to a display device having an external compensation function, the occurrence of operational failure caused by off-leakage at a transistor is suppressed. A unit circuit configuring a gate driver is provided with a stabilization transistor including a control terminal, a first conduction terminal connected to a first internal node, and a second conduction terminal connected to a first control signal line, a stabilization circuit-configured to control a potential of the control terminal of the stabilization transistor-based on a potential of the first internal node, a first reset transistor including a control terminal, a first conduction terminal connected to a second output terminal, and a second conduction terminal connected to a first reference potential line, and a reset circuit configured to control a potential of the control terminal of the first reset transistor based on the potential of the first internal node.

Abstract: An active matrix substrate is provided with a demultiplexer circuit. Each unit circuit of the demultiplexer circuit splits the display signal from a single signal output line to n source bus lines. Each unit circuit includes n branch lines and n switching TFTs. The demultiplexer circuit includes boost circuits configured to boost the voltage applied to the gate electrodes of the switching TFTs. Each boost circuit includes a set section that pre-charges a node connected to the gate electrode, a boost section that boosts the potential of the node pre-charged by the set section, and a reset section that resets the potential of the node. The demultiplexer circuit includes an equalizer circuit configured to perform charge sharing by electrically connecting a first node boosted by the boost section of a first boost circuit and a second node boosted by the boost section of a second boost circuit.

Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

Abstract: An X-ray fluoroscopic imaging apparatus includes first slide mechanism is disposed at a lower end of a support column, and a second slide mechanism is disposed at an upper end of the support column. When an operation unit has received an instruction, a controller performs a first mode in which the X-ray generator is moved in the predetermined direction by operating the second slide mechanism to move an X-ray support arm in the predetermined direction with respect to the upper end of the support column. Thereafter, the controller performs a second mode of operating the first slide mechanism to move the lower end of the support column at a predetermined first speed in the predetermined direction with respect to a support column support arm, while operating the second slide mechanism to move the X-ray support arm at a second speed smaller than the first speed in an opposite direction.

Abstract: In a plasma deposition method, a substrate is loaded onto a substrate stage within a chamber. A first plasma is generated at a region separated from the substrate by a first distance. A first process gas is supplied to the first plasma region to perform a pre-treatment process on the substrate. A second plasma is generated at a region separated from the substrate by a second distance different from the first distance. A second process gas is supplied to the second plasma region to perform a deposition process on the substrate.

Abstract: An active matrix substrate according to an embodiment of the present invention includes: a plurality of source bus lines provided on a substrate; a source driver disposed in a peripheral region; signal output lines each connected to a corresponding one of output terminals of the source driver; and a demultiplexer circuit disposed in a peripheral region. The demultiplexer circuit includes unit circuits each configured to distribute a display signal from one signal output line to n source bus lines (n is an integer larger than or equal to 2). Each unit circuit includes n switching TFTs configured to perform individual on/off control of electrical connections of the n branch lines to the n source bus lines. The n branch lines being connected to one signal output lines. The demultiplexer circuit further includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the n switching TFTs.

Abstract: Provided are apparatuses for manufacturing semiconductor devices. An apparatus includes a reaction chamber having a stage to be loaded on a substrate, wherein set plasma is formed over the stage, a plurality of gas supply lines connected to the reaction chamber, flow controllers formed on the plurality of gas supply lines, respectively, to control the amount of a gas supplied to the reaction chamber, and a gas splitter configured to supply a mixed gas to the flow controllers. The apparatus may be a thin film deposition apparatus using plasma and further include a flow control unit connected to the gas splitter and a gas supply source connected to the flow control unit.

Abstract: Provided is a method of forming graphene. The method of forming graphene includes treating a surface of a substrate placed in a reaction chamber with plasma while applying a bias to the substrate, and growing graphene on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD).

Abstract: The jewelry member according to the present disclosure includes: a plurality of spherical bodies that are three-dimensionally arranged regularly and include an amorphous silicic acid; and a resin that is located in a gap among adjacent spherical bodies of the plurality of spherical bodies and includes a fluorescent dye.

Abstract: An active matrix substrate according to an embodiment of the present invention includes: a plurality of source bus lines provided on a substrate; a source driver disposed in a peripheral region; signal output lines each connected to a corresponding one of output terminals of the source driver; and a demultiplexer circuit disposed in a peripheral region. The demultiplexer circuit includes unit circuits each configured to distribute a display signal from one signal output line to n source bus lines (n is an integer larger than or equal to 2). Each unit circuit includes n switching TFTs configured to perform individual on/off control of electrical connections of the n branch lines to the n source bus lines. The n branch lines being connected to one signal output lines. The demultiplexer circuit further includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the n switching TFTs.

Abstract: Provided is an active matrix substrate (100) that includes multiple pixel TFTs (10), multiple gate wiring lines (GL) along which a scanning signal is supplied to the multiple pixel TFTs, multiple source wiring lines (SL) along which a display signal is supplied to the multiple pixel TFTs, a gate driver (20) that drives multiple gate wiring lines, and a source driver (30) that drives multiple source wiring lines. At least one of the gate driver and the source driver includes a current mirror circuit (70). The current mirror circuit is configured with two oxide semiconductor TFTs (71c and 72c) each of which includes an oxide semiconductor layer.

Abstract: An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region. Each unit circuit in the demultiplexer circuit includes n switching TFTs. The demultiplexer circuit includes a boost circuit capable of boosting a voltage applied to a gate electrode of the switching TFT. The boost circuit includes a set unit configured to perform a set action, a boost unit configured to perform a boost action, and a reset unit configured to perform a reset action. The set unit includes a setting TFT including a drain electrode connected to the drive signal line and a source electrode connected to a node connected to the gate electrode of the switching TFT. When the set unit performs the set action, a first signal voltage is supplied from the drive signal line to the drain electrode of the setting TFT, and a second signal voltage higher than the first signal voltage is supplied to the gate electrode of the setting TFT.

Abstract: An active matrix substrate is provided with a demultiplexer circuit. Each unit circuit of the demultiplexer circuit splits the display signal from a single signal output line to n source bus lines. Each unit circuit includes n branch lines and n switching TFTs. The demultiplexer circuit includes boost circuits configured to boost the voltage applied to the gate electrodes of the switching TFTs. Each boost circuit includes a set section that pre-charges a node connected to the gate electrode, a boost section that boosts the potential of the node pre-charged by the set section, and a reset section that resets the potential of the node. The demultiplexer circuit includes an equalizer circuit configured to perform charge sharing by electrically connecting a first node boosted by the boost section of a first boost circuit and a second node boosted by the boost section of a second boost circuit.

Abstract: The active matrix substrate includes a demultiplexer circuit disposed in a peripheral region. Unit circuits of the demultiplexer circuit each distribute a display signal from one signal output line to n source bus lines (n: two or greater). Each unit circuit includes n branch lines and n switching TFTs configured to perform individual on/off control of electrical connections of the branch lines to the source bus lines. The demultiplexer circuit includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the switching TFTs. Each boost circuit includes: a set-and-reset unit configured to perform set operation of pre-charging a node connected to the gate electrode and reset operation of resetting the potential of the node at different timings; and a boost unit configured to perform boost operation of boosting the potential of the node pre-charged by the set operation.

Abstract: The display device includes drive circuits 301 provided in correspondence to the gate lines, respectively, and alternately switches a scanning period for scanning the gate lines and a non-scanning period during one vertical scanning period. The drive circuit 301 includes netA(n), an output switching element M5 connected to netA(n), and a reset circuit R. The output switching element M5 applies a selection voltage to the gate line GLn. The potential of netA(n) changes between a first potential that is equal to or higher than a threshold voltage of the output switching element M5, and a second potential that is lower than the first potential. In the drive circuit 301 wherein a period while netA(n) thereof has the second potential overlaps with the non-scanning period, the reset circuit R resets the potential of netA(n) to the second potential, before the resumption of the scanning period after the non-scanning period.