Patents by Inventor Kaoru Yamamoto

Kaoru Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622437
    Abstract: An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region, and a power source circuit configured to supply power source voltages at a plurality of levels to the demultiplexer circuit. The demultiplexer circuit includes a boost circuit configured to increase a voltage to be applied to a gate electrode of a switching TFT. The boost circuit includes a set up unit to be driven by a first drive signal to pre-charge a node coupled to the gate electrode, a reset unit to be driven by a second drive signal to reset a potential of the node, and a boost unit to be driven by a third drive signal to increase the potential of the node pre-charged by the set up unit. An amplitude of the first drive signal and an amplitude of the second drive signal are identical to each other. An amplitude of the third drive signal differs from the amplitudes of the first drive signal and the second drive signal.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Yamamoto
  • Publication number: 20200105524
    Abstract: Provided is a method of forming graphene. The method of forming graphene includes treating a surface of a substrate placed in a reaction chamber with plasma while applying a bias to the substrate, and growing graphene on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD).
    Type: Application
    Filed: January 29, 2019
    Publication date: April 2, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Keunwook SHIN, Changhyun KIM, Kaoru YAMAMOTO, Changseok LEE, Hyunjae SONG, Eunkyu LEE, Kyung-Eun BYUN, Hyeonjin SHIN, Sungjoo AN
  • Patent number: 10593267
    Abstract: In a current measurement period set in a pause period, a display device of the present invention applies measurement voltages to data lines (S1 to Sm) and measures currents outputted to monitoring lines (M1 to Mm) from m pixel circuits (18), and then applies data voltages generated corresponding to video signals to the data lines (S1 to Sm).
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: March 17, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Daichi Nishikawa, Yasuyuki Ogawa, Kaoru Yamamoto, Noritaka Kishi, Shigetsugu Yamanaka, Masanori Ohara, Noboru Noguchi
  • Publication number: 20200071822
    Abstract: A semiconductor manufacturing, apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is co figured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.
    Type: Application
    Filed: April 1, 2019
    Publication date: March 5, 2020
    Inventors: Sung-Joo An, Jeon-Il Lee, Kaoru Yamamoto, Jang-Hee Lee, Kee-Young Jun, Geun-O Jeong
  • Publication number: 20200075324
    Abstract: In a plasma deposition method, a substrate is loaded onto a substrate stage within a chamber. A first plasma is generated at a region separated from the substrate by a first distance. A first process gas is supplied to the first plasma region to perform a pre-treatment process on the substrate. A second plasma is generated at a region separated from the substrate by a second distance different from the first distance. A second process gas is supplied to the second plasma region to perform a deposition process on the substrate.
    Type: Application
    Filed: April 16, 2019
    Publication date: March 5, 2020
    Inventors: Kaoru YAMAMOTO, Chang-Hyun KIM, Hyun-Jae SONG, Keun-Wook SHIN, Hyeon-Jin SHIN, Sung-Joo AN, Chang-Seok LEE, Kee-Young JUN, Geun-O JEONG, Jang-Hee LEE
  • Patent number: 10571761
    Abstract: An active matrix substrate includes a demultiplexer circuit which includes a plurality of DMX circuit TFTs. Each of the DMX circuit TFTs includes a front-gate electrode (FG) supplied with a control signal from one of a plurality of control signal main lines ASW, BSW and a back-gate electrode (BG) supplied with a back-gate signal which is different from the control signal. The plurality of DMX circuit TFTs includes first DMX circuit TFTs (T1a, T1b) and second DMX circuit TFTs (T2a, T2b). The back-gate electrode of each of the first DMX circuit TFTs (T1a, T1b)is connected with a first back-gate signal main line (BGL(1)) which supplies a first back-gate signal and, the back-gate electrode of each of the second DMX circuit TFTs (T2a, T2b)is connected with a second back-gate signal main line (BGL(2)) which supplies a second back-gate signal which is different from the first back-gate signal.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Akihiro Oda, Tadayoshi Miyamoto
  • Patent number: 10506995
    Abstract: Provided is a mobile X-ray imaging device having a foldable arm unit equipped with an X-ray tube unit, and a storage concave for storing the folded arm unit on the front side of a main body. An end of the arm unit fixed to the main body side is made slidable with respect to the main body. With this configuration, it is possible to provide the mobile X-ray imaging device having a high degree of flexibility in arranging the X-ray tube when imaging is performed, and also the forward view is never be obstructed by the device in transit.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 17, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ninomiya, Katsumi Usami, Masaru Yokoyama, Kazuyuki Yanase, Kaoru Yamamoto
  • Patent number: 10456100
    Abstract: Provided is an X-ray imaging device having a foldable arm unit for supporting an X-ray tube, and an operating unit for operating the X-ray tube, on a joint of arms constituting the arm unit. The operating unit is, for instance, a display unit serving also as the operating unit (display unit with a touch panel), and it is detachable from the joint of the arms. As another operating unit, a handle for operating the arm unit is provided. The handle for operating the arm unit can be provided with an operating switch for operating the X-ray tube. With this configuration, the X-ray imaging device being superior in operability and easy in checking the displayed information can be provided, at any height the X-ray tube is positioned.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 29, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ninomiya, Katsumi Usami, Masaru Yokoyama, Kazuyuki Yanase, Kaoru Yamamoto
  • Publication number: 20190304396
    Abstract: An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region. Each unit circuit in the demultiplexer circuit includes n switching TFTs. The demultiplexer circuit includes a boost circuit capable of boosting a voltage applied to a gate electrode of the switching TFT. The boost circuit includes a set unit configured to perform a set action, a boost unit configured to perform a boost action, and a reset unit configured to perform a reset action. The set unit includes a setting TFT including a drain electrode connected to the drive signal line and a source electrode connected to a node connected to the gate electrode of the switching TFT. When the set unit performs the set action, a first signal voltage is supplied from the drive signal line to the drain electrode of the setting TFT, and a second signal voltage higher than the first signal voltage is supplied to the gate electrode of the setting TFT.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Inventor: Kaoru YAMAMOTO
  • Publication number: 20190305071
    Abstract: An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region, and a power source circuit configured to supply power source voltages at a plurality of levels to the demultiplexer circuit. The demultiplexer circuit includes a boost circuit configured to increase a voltage to be applied to a gate electrode of a switching TFT. The boost circuit includes a set up unit to be driven by a first drive signal to pre-charge a node coupled to the gate electrode, a reset unit to be driven by a second drive signal to reset a potential of the node, and a boost unit to be driven by a third drive signal to increase the potential of the node pre-charged by the set up unit. An amplitude of the first drive signal and an amplitude of the second drive signal are identical to each other. An amplitude of the third drive signal differs from the amplitudes of the first drive signal and the second drive signal.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Inventor: Kaoru YAMAMOTO
  • Publication number: 20190250448
    Abstract: Provided is an active matrix substrate (100) that includes multiple pixel TFTs (10), multiple gate wiring lines (GL) along which a scanning signal is supplied to the multiple pixel TFTs, multiple source wiring lines (SL) along which a display signal is supplied to the multiple pixel TFTs, a gate driver (20) that drives multiple gate wiring lines, and a source driver (30) that drives multiple source wiring lines. At least one of the gate driver and the source driver includes a current mirror circuit (70). The current mirror circuit is configured with two oxide semiconductor TFTs (71c and 72c) each of which includes an oxide semiconductor layer.
    Type: Application
    Filed: August 28, 2017
    Publication date: August 15, 2019
    Inventor: Kaoru YAMAMOTO
  • Publication number: 20190228828
    Abstract: Provided is a semiconductor device having a plurality of memory cells (MC1 and MC2), in which each of the plurality of memory cells (MC1 and MC2) includes: a memory transistor (10M) having an oxide semiconductor layer (17M) as an active layer; and a first selection transistor (10S) having a crystalline silicon layer (13S) as the active layer and connected to the memory transistor (10M) in series.
    Type: Application
    Filed: August 28, 2017
    Publication date: July 25, 2019
    Inventor: Kaoru YAMAMOTO
  • Patent number: 10341582
    Abstract: Provided is an active substrate that is capable of performing high-speed scanning for setting specific scan signal lines to be active at the same time. Each of the shift registers (4) in an N-th stage shift register in two shift register blocks (2 and 3) outputs an out signal in such a manner that neighboring scan signal lines (GLn and GLn+1) are active at the same time.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 2, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Yamamoto
  • Patent number: 10278668
    Abstract: Provided is a mobile X-ray apparatus that is capable of safely charging multiple mobile X-ray apparatuses. A power supply device 10 includes a plug 7; an electrical outlet 8; a battery 12; a control unit 20; a current detector 26; and a power supply circuit 30. The power supply circuit 30 includes a power limiting circuit 40; an external output circuit 50; and a charging circuit 60. The power limiting circuit 40 limits power together with the control unit 20. In the power supply circuit 30, i) if an external output circuit 50 side is current-limited, charging is preferentially performed, and ii) if the charging circuit 60 side is current-limited, power is output preferentially to external equipment. In the power supply circuit 30, the current of one current path is limited, and a large amount of current is allowed to flow preferentially in the other current path.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: May 7, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Shingo Hishikawa, Kaoru Yamamoto, Masakazu Okabe
  • Patent number: 10276122
    Abstract: In a forward shift operation, a second input signal having a higher voltage than a voltage of a first input signal is input to a second gate terminal in a case that a first gate terminal of a first transistor is charged, and a fourth input signal having a higher voltage than a voltage of a third input signal is input to a third gate terminal in a case that the first gate terminal of the first transistor is discharged. In a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Yasuyuki Ogawa
  • Publication number: 20190114984
    Abstract: A display device includes a display panel including gate lines, and drive circuits sequentially scanning the gate lines and supplied with any of M-phase (M: three or greater) drive signals having different phases and a first potential or a second potential (lower) at predetermined cycles. The drive circuit includes netA(n) whose potential changes by one drive signal with the first/second potential as reference, and an output circuit switching a corresponding gate line to a selected/unselected state and including at least one first output switch including a gate connected to netA(n+1) of a first drive circuit different from the drive circuit, a drain supplied with the drive signal, and a source connected to the gate line. Difference between the potential of netA(n+1) in case of switching the gate line to the unselected/selected state and the reference potential in netA(n+1) is equal to difference between the first and second potentials or greater.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 18, 2019
    Inventors: KOHHEI TANAKA, TOKIHIRO YOKONO, KAORU YAMAMOTO
  • Publication number: 20190116324
    Abstract: Provided is an active substrate that is capable of performing high-speed scanning for setting specific scan signal lines to be active at the same time. Each of the shift registers (4) in an N-th stage shift register in two shift register blocks (2 and 3) outputs an out signal in such a manner that neighboring scan signal lines (GLn and GLn+1) are active at the same time.
    Type: Application
    Filed: March 23, 2017
    Publication date: April 18, 2019
    Inventor: KAORU YAMAMOTO
  • Publication number: 20190096353
    Abstract: The display device includes drive circuits 301 provided in correspondence to the gate lines, respectively, and alternately switches a scanning period for scanning the gate lines and a non-scanning period during one vertical scanning period. The drive circuit 301 includes netA(n), an output switching element M5 connected to netA(n), and a reset circuit R. The output switching element M5 applies a selection voltage to the gate line GLn. The potential of netA(n) changes between a first potential that is equal to or higher than a threshold voltage of the output switching element M5, and a second potential that is lower than the first potential. In the drive circuit 301 wherein a period while netA(n) thereof has the second potential overlaps with the non-scanning period, the reset circuit R resets the potential of netA(n) to the second potential, before the resumption of the scanning period after the non-scanning period.
    Type: Application
    Filed: September 28, 2018
    Publication date: March 28, 2019
    Inventors: KOHHEI TANAKA, KAORU YAMAMOTO, TOKIHIRO YOKONO
  • Publication number: 20190080658
    Abstract: Provided is a technique of causing less display irregularities to occur when the scanning of the gate lines is resumed in a display device in which the scanning of gate lines is performed intermittently. A display device includes a display panel, and a driving circuitry that includes a plurality of drive circuits for scanning gate lines. The driving circuitry alternately switches a scanning period in which the gate lines are scanned, and a non-scanning period in which the scanning of the gate lines is suspended, during one vertical scanning period, according to a control signal. Each driving circuit 301n includes a first switching element N that applies a selection voltage to the gate line; an internal line netA; a second switching element A that charges the internal line netA to a first potential; and a third switching element B that includes a drain electrode connected to the internal line netA, and a source electrode having a second potential that is lower than the first potential.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 14, 2019
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: KAORU YAMAMOTO, KOHHEI TANAKA, TOKIHIRO YOKONO
  • Publication number: 20190079330
    Abstract: An active matrix substrate includes a demultiplexer circuit which includes a plurality of DMX circuit TFTs. Each of the DMX circuit TFTs includes a front-gate electrode (FG) supplied with a control signal from one of a plurality of control signal main lines ASW, BSW and a back-gate electrode (BG) supplied with a back-gate signal which is different from the control signal. The plurality of DMX circuit TFTs includes first DMX circuit TFTs (T1a, T1b) and second DMX circuit TFTs (T2a, T2b). The back-gate electrode of each of the first DMX circuit TFTs (T1a, T1b)is connected with a first back-gate signal main line (BGL(1)) which supplies a first back-gate signal and, the back-gate electrode of each of the second DMX circuit TFTs (T2a, T2b)is connected with a second back-gate signal main line (BGL(2)) which supplies a second back-gate signal which is different from the first back-gate signal.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 14, 2019
    Inventors: Kaoru YAMAMOTO, Akihiro ODA, Tadayoshi MIYAMOTO