Patents by Inventor Karthik Balakrishnan

Karthik Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TWIN GATE FIELD EFFECT DIODE
    Publication number: 20190051748
    Abstract: A semiconductor diode including a first conductivity type region on an upper surface of a semiconductor substrate, a fin structure atop the first conductivity type region providing a vertically orientated semiconductor base region, and a second conductivity type region at a second end of the fin structure opposite a first end of the fin structure that is in contact with the first conductivity type region. The semiconductor diode may also include a vertically orientated dual gate that is present around the fin structure. The vertically orientated dual gate including a first gate structure that is present abutting the semiconductor substrate and a second gate structure that is in closer proximity to the second conductivity type region than the first conductivity type region. The first gate structure separated from the second gate structure by a dielectric inter-gate spacer.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • STACKED ELECTROSTATIC DISCHARGE DIODE STRUCTURES
    Publication number: 20190035778
    Abstract: An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure.
    Type: Application
    Filed: August 27, 2018
    Publication date: January 31, 2019
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Tak Ning
  • TILTED NANOWIRE TRANSISTOR
    Publication number: 20190035940
    Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.
    Type: Application
    Filed: July 26, 2017
    Publication date: January 31, 2019
    Inventors: Pouya Hashemi, Kangguo Cheng, Alexander Reznicek, Karthik Balakrishnan
  • LOW VOLTAGE (POWER) JUNCTION FET WITH ALL-AROUND JUNCTION GATE
    Publication number: 20190035787
    Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
    Type: Application
    Filed: May 30, 2018
    Publication date: January 31, 2019
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER
    Publication number: 20190027471
    Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.
    Type: Application
    Filed: September 26, 2018
    Publication date: January 24, 2019
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Nano-sheet transistors with different threshold voltages
    Patent number: 10177235
    Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Superhydrophobic electrode and biosensing device using the same
    Patent number: 10175192
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Vertical schottky contact FET
    Patent number: 10170619
    Abstract: A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is improved. The vertical Schottky contact transistor includes a bottom Schottky contact source/drain structure and a top Schottky contact source/drain structure located at opposing ends of a semiconductor channel region. The bottom Schottky contact source/drain structure includes a base portion and a vertically extending portion.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Vertical field-effect-transistors having multiple threshold voltages
    Patent number: 10170469
    Abstract: Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Digital alloy germanium heterojunction solar cell
    Patent number: 10170660
    Abstract: A photovoltaic device includes a digital alloy buffer layer including a plurality of alternating layers of semiconductor material. An absorption layer epitaxially is grown on the digital alloy buffer layer, an intrinsic layer is formed on the absorption layer and a doped layer is formed on the intrinsic layer. A conductive contact is formed on the doped layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Co-fabrication of vertical diodes and fin field effect transistors on the same substrate
    Patent number: 10170465
    Abstract: A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Superlattice lateral bipolar junction transistor
    Patent number: 10170302
    Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Compound semiconductor devices having buried resistors formed in buffer layer
    Patent number: 10170464
    Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • DEFORMABLE AND FLEXIBLE CAPACITOR
    Publication number: 20180374916
    Abstract: A method for forming a capacitive device comprises forming a first dielectric layer on a substrate. Portions of the first dielectric layer are removed to for form a cavity in the first dielectric layer. A first layer of conductive material is deposited on the first dielectric layer and conformally along sidewalls of the cavity. The method further includes depositing a second dielectric layer on the first layer of conductive material, and depositing a second layer of conductive material on the second dielectric layer to form a capacitive device.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Alexander Reznicek
  • Tapered vertical FET having III-V channel
    Patent number: 10164092
    Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • VERTICAL TRANSISTOR GATED DIODE
    Publication number: 20180366557
    Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.
    Type: Application
    Filed: April 18, 2018
    Publication date: December 20, 2018
    Inventors: Karthik Balakrishnan, Alexander Reznicek
  • DIGITAL ALLOY VERTICAL LAMELLAE FINFET WITH CURRENT FLOW IN ALLOY LAYER DIRECTION
    Publication number: 20180358441
    Abstract: After forming semiconductor fins including vertically oriented alternating first digital alloy sublayer portions comprised of SiGe and second digital alloy sublayer portions comprised of Si on sidewalls of a sacrificial fin located on a substrate, the sacrificial fin is removed, leaving the semiconductor fins protruding from a top surface of the substrate. The SiGe and Si digital alloy sublayer portions are formed using isotopically enriched Si and Ge source gases to minimize isotopic mass variation in the SiGe and Si digital alloy sublayer portions.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 13, 2018
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • FOUR TERMINAL STACKED COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTORS
    Publication number: 20180358476
    Abstract: A semiconductor device that is composed of an epitaxial semiconductor material stacked structure that includes a first epitaxial channel for a first junction field effect transistor (JFET) atop a supporting substrate and a second epitaxial channel region for a second junction field effect transistor (JFET). A commonly electrically contacted source/drain region for each of the first JFET and the second JFET is positioned at an interface of the first and second epitaxial channel region. A channel length for each of the first and second is substantially perpendicular to an upper surface of the supporting substrate. An epitaxial semiconductor gate conductor in direct contact with each of said first epitaxial channel region and the second epitaxial channel region.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Tak H. Ning, Alexander Reznicek
  • CONTACT FORMATION ON GERMANIUM-CONTAINING SUBSTRATES USING HYDROGENATED SILICON
    Publication number: 20180350936
    Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.
    Type: Application
    Filed: August 7, 2018
    Publication date: December 6, 2018
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • DECOUPLING CAPACITOR ON STRAIN RELAXATION BUFFER LAYER
    Publication number: 20180350816
    Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 6, 2018
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek