Patents by Inventor Karthik Balakrishnan

Karthik Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Twin gate tunnel field-effect transistor (FET)
    Patent number: 10553708
    Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Stacked complementary junction FETs for analog electronic circuits
    Patent number: 10553586
    Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Stacked Vertical Transistor-Based Mask-Programmable ROM
    Publication number: 20200035691
    Abstract: VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 30, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques
    Patent number: 10546928
    Abstract: A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Karthik Balakrishnan, Alexander Reznicek, Mahmoud Khojasteh
  • Vertical transistor transmission gate with adjacent NFET and PFET
    Patent number: 10546857
    Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • System and Method of Grading AI Assets
    Publication number: 20200019824
    Abstract: A method is provided for grading an artificial intelligence (AI) asset. After an AI asset is received for transaction, its performance is evaluated on a specialized task and a baseline of performance is established based on an evaluated state of the AI asset. The AI asset is then graded based on the evaluated performance in a task-environment. A value is ascribed to the AI asset. The AI asset is made available for transaction on an AI asset exchange. A related method is also provided where a second evaluation and grading are performed after the AI asset is trained.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 16, 2020
    Inventors: Ian Collins, Jeffrey Brunet, Karthik Balakrishnan, Yousuf Chowdhary, Karen Chan
  • STACKED NANOSHEET FIELD EFFECT TRANSISTOR FLOATING-GATE EEPROM CELL AND ARRAY
    Publication number: 20200006366
    Abstract: Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.
    Type: Application
    Filed: April 4, 2019
    Publication date: January 2, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau, Tak H. Ning
  • Vertical transistor pass gate device
    Patent number: 10522678
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: December 31, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • LATERAL BIPOLAR JUNCTION TRANSISTOR WITH DUAL BASE REGION
    Publication number: 20190371923
    Abstract: A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: Pouya HASHEMI, Bahman HEKMATSHOARTABARI, Alexander REZNICEK, Karthik BALAKRISHNAN, Jeng-Bang YAU
  • System and Method of AI Asset Exchange
    Publication number: 20190355060
    Abstract: A computer-implemented system is provided for exchange of artificial intelligence (AI) assets through an AI asset exchange. The system includes a preprocessing engine programmed for receiving an AI asset by upload and preprocessing the AI asset for transaction by: anonymizing an owner/transactor of the AI asset; associating a set of identification and description parameters with the AI asset; associating a set of transaction terms with the AI asset; and associating a set of use terms with the AI asset. The system also includes a listing engine programmed for listing the preprocessed AI asset according to the identification and description parameters. The system also includes a transaction engine programmed for mediating a transaction of the AI asset according to the transaction terms. A method of preparing an artificial intelligence (AI) asset for transaction is also provided.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 21, 2019
    Inventors: Ian Collins, Jeffrey Brunet, Karthik Balakrishnan, Yousuf Chowdhary, Karen Chan
  • STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) DEVICES
    Publication number: 20190355830
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • VERY NARROW ASPECT RATIO TRAPPING TRENCH STRUCTURE WITH SMOOTH TRENCH SIDEWALLS
    Publication number: 20190355722
    Abstract: After forming a plurality of semiconductor fins that are separated from one another by trenches on a substrate, the semiconductor fins are fully or partially oxidized to provide semiconductor oxide portions. The volume expansion caused by the oxidation of the semiconductor fins reduces widths of the trenches, thereby providing narrowed trenches for formation of epitaxial semiconductor fins using aspect ratio trapping techniques.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • LOW VOLTAGE (POWER) JUNCTION FET WITH ALL-AROUND JUNCTION GATE
    Publication number: 20190341382
    Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices
    Patent number: 10468503
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • VERTICAL TRANSISTOR PASS GATE DEVICE
    Publication number: 20190312141
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS
    Publication number: 20190312044
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • High density programmable e-fuse co-integrated with vertical FETs
    Patent number: 10438956
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • VERTICAL FIELD EFFECT TRANSISTOR (VFET) PROGRAMMABLE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INVERTER
    Publication number: 20190304968
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface
    Patent number: 10424650
    Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.
    Type: Grant
    Filed: June 16, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Decoupling capacitor on strain relaxation buffer layer
    Patent number: 10424585
    Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek