Patents by Inventor Karthik Balakrishnan

Karthik Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ANALYTICS TO DETERMINE CUSTOMER SATISFACTION
    Publication number: 20190266538
    Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: Karthik Balakrishnan, Keith A. Jenkins, Barry P. Linder
  • Vertical transistor pass gate device
    Patent number: 10396198
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Method and structure for incorporating strain in nanosheet devices
    Patent number: 10396202
    Abstract: A semiconductor structure includes a plurality of stacked and suspended semiconductor nanosheets located above a semiconductor substrate. Each semiconductor nanosheet has a pair of end sidewalls that have a V-shaped undercut surface. A functional gate structure is located around the plurality of stacked and suspended semiconductor nanosheets, and a source/drain (S/D) semiconductor material structure is located on each side of the functional gate structure. In accordance with the present application, sidewall portions of each S/D semiconductor material structure are in direct contact with the V-shaped undercut surface of the end sidewalls of each of the semiconductor nanosheets.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Very narrow aspect ratio trapping trench structure with smooth trench sidewalls
    Patent number: 10396075
    Abstract: After forming a plurality of semiconductor fins that are separated from one another by trenches on a substrate, the semiconductor fins are fully or partially oxidized to provide semiconductor oxide portions. The volume expansion caused by the oxidation of the semiconductor fins reduces widths of the trenches, thereby providing narrowed trenches for formation of epitaxial semiconductor fins using aspect ratio trapping techniques.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • DIODE CONNECTED VERTICAL TRANSISTOR
    Publication number: 20190259750
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • STACKED COMPLEMENTARY JUNCTION FETS FOR ANALOG ELECTRONIC CIRCUITS
    Publication number: 20190259755
    Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • STACKED COMPLEMENTARY JUNCTION FETS FOR ANALOG ELECTRONIC CIRCUITS
    Publication number: 20190259756
    Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Vertical field effect transistor (VFET) programmable complementary metal oxide semiconductor inverter
    Patent number: 10388648
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Stacked complementary junction FETs for analog electronic circuits
    Patent number: 10381349
    Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • System and Method of Chat Orchestrated Visualization
    Publication number: 20190236142
    Abstract: A method is provided for chat orchestrated visualization. In response to a substantive user communication received in the chat session, the system decomposes the terms of the communication into components. From at least one of the components, an intent of the communication is determined and a search is formulated with the intent which is searched in a plurality of data sources to obtain raw search results which are stored in a cache. Natural language understanding (NLU), natural language generation (NLG) or generative neural nets (GNN) may be used to generate a short text response to the user communication, and related web content is synthesized in text and other forms. The short response is displayed in the chat session while the synthesized web content is injected and displayed in a passive window, such that the chat session and the web content are displayed in different portions of the same screen.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 1, 2019
    Inventors: Karthik Balakrishnan, Jeffrey Brunet, Yousuf Chowdhary, Karen Chan, Ian Collins
  • Diode connected vertical transistor
    Patent number: 10366984
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • STRAINED SILICON GERMANIUM FIN WITH BLOCK SOURCE/DRAIN EPITAXY AND IMPROVED OVERLAY CAPACITANCE
    Publication number: 20190229195
    Abstract: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Fabrication of vertical fin transistor with multiple threshold voltages
    Patent number: 10361301
    Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Vertical transistor transmission gate with adjacent NFET and PFET
    Patent number: 10361199
    Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Analytics to determine customer satisfaction
    Patent number: 10360526
    Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Keith A. Jenkins, Barry P. Linder
  • Support for long channel length nanowire transistors
    Patent number: 10354960
    Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita, Jeffrey W. Sleight
  • DIODE CONNECTED VERTICAL TRANSISTOR
    Publication number: 20190214384
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 11, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • MONOLITHIC CO-INTEGRATION OF MOSFET AND JFET FOR NEUROMORPHIC/COGNITIVE CIRCUIT APPLICATIONS
    Publication number: 20190214309
    Abstract: Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • STACKED FINFET EEPROM
    Publication number: 20190214398
    Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Germanium dual-fin field effect transistor
    Patent number: 10347539
    Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek