Patents by Inventor Karthik Balakrishnan

Karthik Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NANOSHEET ONE TRANSISTOR DYNAMIC RANDOM ACCESS DEVICE WITH SILICON/SILICON GERMANIUM CHANNEL AND COMMON GATE STRUCTURE
    Publication number: 20200251474
    Abstract: A memory device is provided that includes a bilayer nanosheet channel layer including a silicon (Si) layer and a silicon germanium (SiGe) layer; and a common gate structure for biasing each of the silicon layer and the silicon germanium layer of the bilayer nanosheet channel layer to provide one of the silicon layer and the silicon germanium layer is biased in accumulation and one of the first layer and the second layer biased in inversion. The memory devices also includes a floating body region on a front face or rear face of the bilayer nanosheet channel layer.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 6, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari, Clint Oteri
  • Lateral bipolar junction transistor with dual base region
    Patent number: 10734505
    Abstract: A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau
  • Method for manufacturing a semiconductor structure including a very narrow aspect ratio trapping trench structure
    Patent number: 10734382
    Abstract: After forming a plurality of semiconductor fins that are separated from one another by trenches on a substrate, the semiconductor fins are fully or partially oxidized to provide semiconductor oxide portions. The volume expansion caused by the oxidation of the semiconductor fins reduces widths of the trenches, thereby providing narrowed trenches for formation of epitaxial semiconductor fins using aspect ratio trapping techniques.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • NANOSHEET RADIATION DOSIMETER
    Publication number: 20200241149
    Abstract: A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 30, 2020
    Inventors: Jeng-Bang Yau, Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari
  • Contact formation on germanium-containing substrates using hydrogenated silicon
    Patent number: 10727310
    Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Diode connected vertical transistor
    Patent number: 10720427
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Fabrication of strained vertical p-type field effect transistors by bottom condensation
    Patent number: 10714593
    Abstract: A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • AREA-EFFICIENT INVERTER USING STACKED VERTICAL TRANSISTORS
    Publication number: 20200212226
    Abstract: An inverter that includes an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) vertically stacked one atop the other and containing a buried metal semiconductor alloy strap that connects a drain region of the nFET to a drain region of the pFET is provided. Also, provided is a cross-coupled inverter pair with nFETs and pFETs stacked vertically.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Inventors: Alexander Reznicek, Kangguo Cheng, Karthik Balakrishnan, Pouya Hashemi
  • TILTED NANOWIRE TRANSISTOR
    Publication number: 20200212228
    Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: Pouya Hashemi, Kangguo Cheng, Alexander Reznicek, Karthik Balakrishnan
  • Compound semiconductor devices having buried resistors formed in buffer layer
    Patent number: 10700058
    Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Large area diode co-integrated with vertical field-effect-transistors
    Patent number: 10692859
    Abstract: An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Analytics to determine customer satisfaction
    Patent number: 10671958
    Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Keith A. Jenkins, Barry P. Linder
  • Deformable and flexible capacitor
    Patent number: 10672865
    Abstract: A method for forming a capacitive device comprises forming a first dielectric layer on a substrate. Portions of the first dielectric layer are removed to for form a cavity in the first dielectric layer. A first layer of conductive material is deposited on the first dielectric layer and conformally along sidewalls of the cavity. The method further includes depositing a second dielectric layer on the first layer of conductive material, and depositing a second layer of conductive material on the second dielectric layer to form a capacitive device.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Alexander Reznicek
  • High density vertically integrated FEOL MIM capacitor
    Patent number: 10672862
    Abstract: A metal-insulator-metal (MIM) capacitor is provided on a surface of an insulator layer that is located on a handle substrate. The MIM capacitor includes a first metal structure extending upwards from a first portion of the insulator layer, a second metal structure extending upwards from a second portion of the insulator layer, and an oxide fin located between the first and second metal structures, wherein the oxide fin directly contacts an entirety of a sidewall surface of the first metal structure and an entirety of a sidewall surface of the second metal structure, the oxide fin having a topmost surface that is coplanar with a topmost surface of both the first and second metal structures.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • STACKED FINFET PROGRAMMABLE INVERTER (EPROM)
    Publication number: 20200161323
    Abstract: A stacked FinFET programmable inverter is provided that includes a pFET gate structure including a floating gate and a thicker gate dielectric material layer than a gate dielectric material layer of an nFET gate structure stacked either above, or below, the nFET gate structure. In one embodiment, the pFET gate structure is below the nFET gate structure. In another embodiment, the pFET gate structure is above the nFET gate structure. The pFET gate structure contacts a sidewall of one semiconductor fin portion of a fin stack, while the nFET gate structure contacts a sidewall of another of the semiconductor fin portion of the same fin stack; the two semiconductor fin portions are separated by an insulator fin portion.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • Stacked electrostatic discharge diode structures
    Patent number: 10658353
    Abstract: An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Tak Ning
  • Vertical transistor pass gate device
    Patent number: 10658507
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • DIODE CONNECTED VERTICAL TRANSISTOR
    Publication number: 20200152624
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • SUPERHYDROPHOBIC ELECTRODE AND BIOSENSING DEVICE USING THE SAME
    Publication number: 20200141899
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Digital alloy vertical lamellae FinFET with current flow in alloy layer direction
    Patent number: 10644109
    Abstract: After forming semiconductor fins including vertically oriented alternating first digital alloy sublayer portions comprised of SiGe and second digital alloy sublayer portions comprised of Si on sidewalls of a sacrificial fin located on a substrate, the sacrificial fin is removed, leaving the semiconductor fins protruding from a top surface of the substrate. The SiGe and Si digital alloy sublayer portions are formed using isotopically enriched Si and Ge source gases to minimize isotopic mass variation in the SiGe and Si digital alloy sublayer portions.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek