Patents by Inventor Karthik Balakrishnan

Karthik Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Decoupling capacitor on strain relaxation buffer layer
    Patent number: 10644007
    Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • STACKED FINFET READ ONLY MEMORY
    Publication number: 20200135747
    Abstract: A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. The fin structure includes, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion. A lower gate structure having a first threshold voltage contacts a sidewall of the first semiconductor fin portion, and an upper gate structure having a second threshold voltage contacts a sidewall of the second semiconductor fin portion.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan
  • Stacked FinFET programmable inverter (EPROM)
    Patent number: 10636804
    Abstract: A stacked FinFET programmable inverter is provided that includes a pFET gate structure including a floating gate and a thicker gate dielectric material layer than a gate dielectric material layer of an nFET gate structure stacked either above, or below, the nFET gate structure. In one embodiment, the pFET gate structure is below the nFET gate structure. In another embodiment, the pFET gate structure is above the nFET gate structure. The pFET gate structure contacts a sidewall of one semiconductor fin portion of a fin stack, while the nFET gate structure contacts a sidewall of another of the semiconductor fin portion of the same fin stack; the two semiconductor fin portions are separated by an insulator fin portion.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • THREE-DIMENSIONALLY STRETCHABLE SINGLE CRYSTALLINE SEMICONDUCTOR MEMBRANE
    Publication number: 20200123677
    Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Keith E. Fogel
  • Tilted nanowire transistor
    Patent number: 10622486
    Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Kangguo Cheng, Alexander Reznicek, Karthik Balakrishnan
  • MICROFLUIDIC SYSTEM WITH COMBINED ELECTRICAL AND OPTICAL DETECTION FOR HIGH ACCURACY PARTICLE SORTING AND METHODS THEREOF
    Publication number: 20200096436
    Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.
    Type: Application
    Filed: February 6, 2018
    Publication date: March 26, 2020
    Inventors: Hany NASSEF, Karthik BALAKRISHNAN, Anand KESAVARAJU, Vincent TUMINELLI, George ANWAR
  • Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
    Patent number: 10600878
    Abstract: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • SINGLE COLUMN COMPOUND SEMICONDUCTOR BIPOLAR JUNCTION TRANSISTOR WITH ALL-AROUND BASE
    Publication number: 20200091322
    Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 19, 2020
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Diode connected vertical transistor
    Patent number: 10593669
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Superhydrophobic electrode and biosensing device using the same
    Patent number: 10585063
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Stacked series connected VFETs for high voltage applications
    Patent number: 10580901
    Abstract: A method of forming a semiconductor device and resulting structures having stacked vertical field effect transistors (VFETs) connected in series. A first semiconductor fin and a second semiconductor fin are formed on a doped region of a substrate. A shared gate is formed over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin. A shared epitaxy region is formed on a surface of the first semiconductor fin and a surface of the second semiconductor fin.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • VERTICAL TRANSISTOR PASS GATE DEVICE
    Publication number: 20200066905
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) DEVICES
    Publication number: 20200066875
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) DEVICES
    Publication number: 20200066874
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • Low voltage (power) junction FET with all-around junction gate
    Patent number: 10573648
    Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • System and Method of Quotation Engine for AI Asset Training
    Publication number: 20200057920
    Abstract: A computer-implemented system is provided for automatic training of an artificial intelligence (AI) asset. A preprocessing engine is provided for receiving an AI asset by upload and preprocessing the AI asset for training by: associating a set of definition parameters and training criteria with the AI asset; analyzing the training criteria to set a specification for training steps and process; and determining a quotation for the training having regard to known factors associated with the definition parameters and the training specification. A transaction engine is provided for presenting the quotation, receiving an approval of the quotation and a means of payment. A training engine is provided for training the AI asset according to the specification and releasing the AI asset after training.
    Type: Application
    Filed: August 19, 2019
    Publication date: February 20, 2020
    Inventors: Ian Collins, Jeffrey Brunet, Karthik Balakrishnan, Yousuf Chowdhary, Karen Chan
  • TWIN GATE TUNNEL FIELD-EFFECT TRANSISTOR (FET)
    Publication number: 20200058775
    Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Single column compound semiconductor bipolar junction transistor with all-around base
    Patent number: 10566447
    Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • FinFET with stacked faceted S/D epitaxy for improved contact resistance
    Patent number: 10566349
    Abstract: A semiconductor structure including a multi-faceted epitaxial semiconductor structure within both a source region and a drain region and on exposed surfaces of a semiconductor fin is provided. The multi-faceted epitaxial semiconductor structure includes faceted epitaxial semiconductor material portions located on different portions of each vertical sidewall of the semiconductor fin and a topmost faceted epitaxial semiconductor material portion that is located on an exposed topmost horizontal surface of the semiconductor fin. The multi-faceted epitaxial semiconductor structure has increased surface area and thus an improvement in contact resistance can be obtained utilizing the same.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Twin gate tunnel field-effect transistor (FET)
    Patent number: 10553708
    Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau