Patents by Inventor Karthik Kumar

Karthik Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11451435
    Abstract: Technologies for providing multi-tenant support in edge resources using edge channels include a device that includes circuitry to obtain a message associated with a service provided at the edge of a network. Additionally, the circuitry is to identify an edge channel based on metadata associated with the message. The edge channel has a predefined amount of resource capacity allocated to the edge channel to process the message. Further, the circuitry is to determine the predefined amount of resource capacity allocated to the edge channel and process the message using the allocated resource capacity for the identified edge channel.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 20, 2022
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Benjamin Graniello, Timothy Verrall, Andrew J. Herdrich, Rashmin Patel, Monica Kenguva, Brinda Ganesh, Alexander Vul, Ned M. Smith, Suraj Prabhakaran
  • Publication number: 20220263891
    Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.
    Type: Application
    Filed: March 7, 2022
    Publication date: August 18, 2022
    Inventors: Francesc Guim Bernat, Ned Smith, Thomas Willhalm, Karthik Kumar, Timothy Verrall
  • Patent number: 11416295
    Abstract: Technologies for providing efficient data access in an edge infrastructure include a compute device comprising circuitry configured to identify pools of resources that are usable to access data at an edge location. The circuitry is also configured to receive a request to execute a function at an edge location. The request identifies a data access performance target for the function. The circuitry is also configured to map, based on a data access performance of each pool and the data access performance target of the function, the function to a set of the pools to satisfy the data access performance target.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 16, 2022
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Timothy Verrall, Thomas Willhalm, Mark Schmisseur
  • Patent number: 11409440
    Abstract: Memory controller systems, methods and apparatus for memory access and scheduling are herein disclosed. In some aspects, a memory controller includes a clock, a first interface to be coupled with a first memory device via a common memory channel, and a second interface to be coupled with a second memory device via the common memory channel. The memory controller also includes a register to store data to store data to indicate an access scheme to process access requests to the first memory device according to a first timing scheme and issue access requests to the second memory device according to a second timing scheme. The memory controller further includes logic to cause the access scheme to be implemented in order to issue access requests to the first memory device or to issue access requests to the second memory device via the common memory channel.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: August 9, 2022
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark Schmisseur
  • Patent number: 11412052
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
  • Publication number: 20220222274
    Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.
    Type: Application
    Filed: January 20, 2022
    Publication date: July 14, 2022
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall, Ned Smith
  • Publication number: 20220222010
    Abstract: Methods and apparatus for advanced interleaving techniques for fabric based pooling architectures. The method implemented in an environment including a switch connected to host servers and to pooled memory nodes or memory servers hosting memory pools. Memory is interleaved across the memory pools using interleaving units, with the interleaved memory mapped into a global memory address space. Applications running on the host servers are enabled to access data stored in the memory pools via memory read and write requests issued by the applications specifying address endpoints within the global memory space. The switch generates multi-cast or multiple unicast messages associated with the memory read and write requests that are sent to the pooled memory nodes or memory servers. For memory reads, the data returned from multiple memory pools is aggregated at the switch and returned to the application using one or more packets as a single response.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: Alexander BACHMUTSKY, Francesc GUIM BERNAT, Karthik KUMAR, Marcos E. CARRANZA
  • Publication number: 20220219032
    Abstract: Commissioning a fire system is described herein. One embodiment includes a non-transitory machine-readable medium having instructions stored thereon which, when executed by a processor, cause the processor to receive an indicator of a particular fire control panel of a fire system installed in a building, and provide an interface via a display for configuring a gateway device associated with the fire control panel responsive to receiving the indicator, the interface including a plurality of portions, wherein each portion is configured to receive a respective descriptor corresponding to the fire control panel.
    Type: Application
    Filed: January 12, 2021
    Publication date: July 14, 2022
    Inventors: Deepika Sahai, Amit Jain, Karthik Kumar Davanam
  • Publication number: 20220224657
    Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.
    Type: Application
    Filed: October 25, 2021
    Publication date: July 14, 2022
    Inventors: Francesc Guim Bernat, Anil Rao, Suraj Prabhakaran, Mohan Kumar, Karthik Kumar
  • Publication number: 20220210073
    Abstract: Technologies for load balancing on a network device in an edge network are disclosed. An example network device includes circuitry to receive, in an edge network, a request to access a function, the request including one or more performance requirements, identify, as a function of an evaluation of the performance requirements and on monitored properties of each of a plurality of devices associated with the network device, one or more of the plurality of devices to service the request, select one of the identified devices according to a load balancing policy, and send the request to the selected device.
    Type: Application
    Filed: January 4, 2022
    Publication date: June 30, 2022
    Inventors: Francesc Guim Bernat, Karthik Kumar, Ned M. Smith, Monica Kenguva, Rashmin Patel
  • Publication number: 20220206857
    Abstract: Technologies for providing dynamic selection of edge and local accelerator resources includes a device having circuitry to identify a function of an application to be accelerated, determine one or more properties of an accelerator resource available at the edge of a network where the device is located, and determine one or more properties of an accelerator resource available in the device. Additionally, the circuitry is to determine a set of acceleration selection factors associated with the function, wherein the acceleration factors are indicative of one or more objectives to be satisfied in the acceleration of the function. Further, the circuitry is to select, as a function of the one or more properties of the accelerator resource available at the edge, the one or more properties of the accelerator resource available in the device, and the acceleration selection factors, one or more of the accelerator resources to accelerate the function.
    Type: Application
    Filed: November 8, 2021
    Publication date: June 30, 2022
    Inventors: Francesc Guim Bernat, Karthik Kumar, Ned Smith, Thomas Willhalm, Timothy Verrall
  • Publication number: 20220206849
    Abstract: Methods and apparatus for hardware support for low latency microservice deployments in switches. A switch is communicatively coupled via a network or fabric to a plurality of platforms configured to implement one or more microservices. The microservices are used to perform a distributed workload, job, or task as defined by a corresponding graph representation of the microservices including vertices (also referred to as nodes) associated with microservices and edges defining communication between microservices. The graph representation also defines dependencies between microservices. The switch is configured to schedule execution of the graph of microservices on the plurality of platforms, including generating an initial schedule that is dynamically revised during runtime in consideration of performance telemetry data for the microservices received from the platforms and network/fabric utilization monitored onboard the switch.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Inventors: Francesc GUIM BERNAT, Karthik KUMAR, Alexander BACHMUTSKY
  • Publication number: 20220197819
    Abstract: Examples described herein relate to a memory controller to allocate an address range for a process among multiple memory pools based on a service level parameters associated with the address range and performance capabilities of the multiple memory pools. In some examples, the service level parameters include one or more of latency, network bandwidth, amount of memory allocation, memory bandwidth, data encryption use, type of encryption to apply to stored data, use of data encryption to transport data to a requester, memory technology, and/or durability of a memory device.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Inventors: Karthik KUMAR, Francesc GUIM BERNAT, Thomas WILLHALM, Marcos E. CARRANZA, Cesar Ignacio MARTINEZ SPESSOT
  • Publication number: 20220197729
    Abstract: An apparatus comprising a network interface controller comprising a queue for messages for a thread executing on a host computing system, wherein the queue is dedicated to the thread; and circuitry to send a notification to the host computing system to resume execution of the thread when a monitoring rule for the queue has been triggered.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Patrick G. Kutch, Alexander Bachmutsky, Nicolae Octavian Popovici
  • Publication number: 20220200788
    Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 23, 2022
    Inventors: Timothy Verrall, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar, Ned M. Smith, Rajesh Poornachandran, Kapil Sood, Tarun Viswanathan, John J. Browne, Patrick Kutch
  • Patent number: 11366782
    Abstract: An apparatus is described. The apparatus includes logic circuitry embedded in at least one of a memory controller, network interface and peripheral control hub to process a function as a service (FaaS) function call embedded in a request. The request is formatted according to a protocol. The protocol allows a remote computing system to access a memory that is coupled to the memory controller without invoking processing cores of a local computing system that the memory controller is a component of.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mustafa Hajeer
  • Patent number: 11354329
    Abstract: A system for mining of real-time data from non-production environments (e.g., test and development environments). The data that is mined/extracted is “live” data that reflects instantaneous changes, modifications, to the data. In addition, since embodiments of the present invention provide users/testers with a “live” real-time view of the mined data, the data is stored in temporary storage/non-cache memory as opposed to permanent storage (i.e., cache memory). As a result, once the user/tester consumes the data (i.e., modifies, changes or otherwise conditions the data), the data is deleted from the temporary/non-cache storage location. Thus, embodiments of the invention eliminate the need to provide for and maintain a large database for permanent storage of mined test data.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: June 7, 2022
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Sujata Devon Raju, Vinod Kumar Alladi, Bhimeswar Rao Kharade Maratha, Jayadev Mynampati, Parthiban Tiruvayur Shanmugam, Durga Prasad Turaga, Karthik Kumar Venkatasubramanian
  • Publication number: 20220166846
    Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.
    Type: Application
    Filed: July 30, 2021
    Publication date: May 26, 2022
    Inventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
  • Publication number: 20220166847
    Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.
    Type: Application
    Filed: December 3, 2021
    Publication date: May 26, 2022
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Petar Torre, Ned Smith, Brinda Ganesh, Evan Custodio, Suraj Prabhakaran
  • Patent number: 11343177
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta