Patents by Inventor Karthik Kumar

Karthik Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230325246
    Abstract: A platform includes a plurality of hardware blocks to provide respective functionality for use in execution of an application. A subset of the plurality of hardware blocks are deactivated and unavailable for use in the execution of the application at the start of the execution of the application. A hardware profile modification block of the platform identifies receives telemetry data generated by a set of sensors and dynamically activates at least a particular one of the subset of hardware blocks based on the physical characteristics, where following activation of the particular hardware block, the execution of the application continues and uses the particular hardware block.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 12, 2023
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, John J. Browne, Amruta Misra, Chris M. MacNamara
  • Patent number: 11768705
    Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device which is enabled to access and select the use of local or remote acceleration resources for edge computing processing is disclosed. In an example, an edge computing device obtains first telemetry information that indicates availability of local acceleration circuitry to execute a function, and obtains second telemetry that indicates availability of a remote acceleration function to execute the function. An estimated time (and cost or other identifiable or estimateable considerations) to execute the function at the respective location is identified. The use of the local acceleration circuitry or the remote acceleration resource is selected based on the estimated time and other appropriate factors in relation to a service level agreement.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Ned M. Smith, Thomas Willhalm, Timothy Verrall
  • Publication number: 20230281113
    Abstract: Techniques for adaptive memory metadata allocation. A processor may determine a first memory region of a plurality of memory regions in a memory pool coupled to the processor via an interface. The processor may modify a metadata of the first memory region from a first configuration to a second configuration, where the first configuration is associated with a first number of error correction code (ECC) bits and the second configuration is associated with a second number of ECC bits.
    Type: Application
    Filed: April 7, 2023
    Publication date: September 7, 2023
    Applicant: INTEL CORPORATION
    Inventors: Karthik Kumar, Francesc Guim Bernat, Ramamurthy Krithivas
  • Publication number: 20230240055
    Abstract: Methods and apparatus to manage noise in computing systems are disclosed. An example server includes a housing to at least partially contain components of the server, a transducer to output an indication of noise detected outside of the housing, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to adjust the operation of the server based on the output of the transducer to reduce noise.
    Type: Application
    Filed: March 31, 2023
    Publication date: July 27, 2023
    Inventors: Francesc Guim Bernat, Karthik Kumar, Marcos Carranza
  • Patent number: 11706158
    Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Anil Rao, Suraj Prabhakaran, Mohan Kumar, Karthik Kumar
  • Publication number: 20230222025
    Abstract: Reliability, availability, and serviceability (RAS)-based memory domains can enable applications to store data in memory domains having different degrees of reliability to reduce downtime and data corruption due to memory errors. In one example, memory resources are classified into different RAS-based memory domains based on their expected likelihood of encountering errors. The mapping of memory resources into RAS-based memory domains can be dynamically managed and updated when information indicative of reliability (such as the occurrence of errors or other information) suggests that a memory resource is becoming less reliable. The RAS-based memory domains can be exposed to applications to enable applications to allocate memory in high reliability memory for critical data.
    Type: Application
    Filed: March 21, 2023
    Publication date: July 13, 2023
    Inventors: Karthik KUMAR, Francesc GUIM BERNAT, Mark A. SCHMISSEUR, Thomas WILLHALM, Marcos E. CARRANZA
  • Publication number: 20230205604
    Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 29, 2023
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Ignacio Astilleros Diez, Timothy Verrall, Ned M. Smith
  • Publication number: 20230205652
    Abstract: Embodiments described herein are generally directed to intelligent management of microservices failover. In an example, responsive to an uncorrectable hardware error associated with a processing resource of a platform on which a task of a service is being performed by a primary microservice, a failover trigger is received by a failover service. A secondary microservice is identified by the failover service that is operating in lockstep mode with the primary microservice. The secondary microservice is caused by the failover service to takeover performance of the task in non-lockstep mode based on failover metadata persisted by the primary microservice. The primary microservice is caused by the failover service to be taken offline.
    Type: Application
    Filed: December 7, 2022
    Publication date: June 29, 2023
    Applicant: Intel Corporation
    Inventors: Rajesh Poornachandran, Marcos Carranza, Kshitij Arun Doshi, Francesc Guim Bernat, Karthik Kumar
  • Publication number: 20230198875
    Abstract: An apparatus to facilitate at-scale telemetry using interactive matrix for deterministic microservices performance is disclosed. The apparatus includes one or more processors to: receive user input comprising an objective or task corresponding to scheduling a microservice for a service, wherein the objective or task may include QoS, SLO, ML feedback; identify interaction matrix components in an interaction matrix that match the objective or tasks for the microservice; identify knowledgebase components in knowledgebase that match the objective or tasks for the microservice; and determine a scheduling operation for the microservice, the scheduling operation to deploy the microservice in a configuration that is in accordance with the objective or task, wherein the configuration comprises a set of hardware devices and microservice interaction points determined based on the interaction matrix components and the knowledgebase components.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Rajesh Poornachandran, Vincent Zimmer, Subrata Banik, Marcos Carranza, Kshitij Arun Doshi, Francesc Guim Bernat, Karthik Kumar
  • Publication number: 20230198959
    Abstract: Embodiments described herein are generally directed to a transparent and adaptable mechanism for performing secure application communications through sidecars. In an example, a set of security features is discovered by a first sidecar of a first microservice of multiple microservices of an application. The set of security features are associated with a device of multiple devices of a set of one or more host systems on which the first microservice is running. Information regarding the set of discovered security features is made available to the other microservices by the first sidecar by sharing the information with a discovery service accessible to all of the microservices. A configuration of a communication channel through which a message is to be transmitted from a second microservice to the first microservice is determined by a second sidecar of the second microservice by issuing a request to the discovery service regarding the first microservice.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Cesar Martinez-Spessot, Marcos Carranza, Lakshmi Talluru, Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Rajesh Poornachandran, Kshitij Arun Doshi
  • Publication number: 20230199077
    Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to: obtain, by a microservice of a service hosted in a datacenter, provisioned credentials for the microservice based on an attestation protocol; generate, for a task performed by the microservice, provenance metadata for the task, the provenance metadata including identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and operating state of a sidecar of the microservice during the task; encrypt the provenance metadata with the provisioned credentials for the microservice; and record the encrypted provenance metadata in a local blockchain of provenance metadata maintained for the hardware resource executing the task and the microservice.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Rajesh Poornachandran, Vincent Zimmer, Subrata Banik, Marcos Carranza, Kshitij Arun Doshi, Francesc Guim Bernat, Karthik Kumar
  • Publication number: 20230195547
    Abstract: Embodiments described herein are generally directed to the use of sidecars to perform dynamic API contract generation and conversion. In an example, a first call by a first microservice to a first API of a second microservice is intercepted by a first sidecar of the first microservice. The first API is of a first API type of multiple API types and is specified by a first contract. An API type of the multiple API types is selected by the first sidecar. Responsive to determining the selected API type differs from the first API type, based on the first contract, a second contract is generated by the first sidecar specifying a second API of the selected API type; and a second sidecar of the second microservice is caused to generate the second API and internally connect the second API to the first API based on the second contract.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Marcos Carranza, Cesar Martinez-Spessot, Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Rajesh Poornachandran, Kshitij Arun Doshi
  • Publication number: 20230195597
    Abstract: An apparatus to facilitate matchmaking-based enhanced debugging for microservices architectures is disclosed. The apparatus includes one or more processors to: detect, by an anomaly detector in a sidecar of a microservice hosted by a container, an anomaly in telemetry data generated by the microservice, the microservice hosted in a container executed by the processor and part of a service of an application; enable, by an enhanced debug and trace component of the sidecar, a debug mode in the microservice, the debug mode based on a type of the anomaly; collect, by the enhanced debug and trace component, a target set of data points generated by the microservice; and process, by the enhanced debug and trace component, the target set of data points with a matchmaking process to generate a timestamp and a tag for a context for each data point of the target set of data points.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Marcos Carranza, Cesar Martinez-Spessot, Rajesh Poornachandran, Kshitij Arun Doshi
  • Patent number: 11675326
    Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Nicolas A. Salhuana, Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Narayan Ranganathan
  • Patent number: 11650951
    Abstract: An apparatus is described. The apparatus includes logic circuitry embedded in at least one of a memory controller, network interface and peripheral control hub to process a function as a service (FaaS) function call embedded in a request. The request is formatted according to a protocol. The protocol allows a remote computing system to access a memory that is coupled to the memory controller without invoking processing cores of a local computing system that the memory controller is a component of.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mustafa Hajeer
  • Publication number: 20230142539
    Abstract: Example edge gateway circuitry to schedule service requests in a network computing system includes: gateway-level hardware queue manager circuitry to: parse the service requests based on service parameters in the service requests; and schedule the service requests in a queue based on the service parameters, the service requests received from client devices; and hardware queue manager communication interface circuitry to send ones of the service requests from the queue to rack-level hardware queue manager circuitry in a physical rack, the ones of the service requests corresponding to functions as a service provided by resources in the physical rack.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 11, 2023
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ignacio Astilleros Diez, Timothy Verrall
  • Publication number: 20230135645
    Abstract: Various approaches for deploying and controlling distributed compute operations with the use of infrastructure processing units (IPUs) and similar networked processing units are disclosed.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Inventors: Francesc Guim Bernat, Karthik Kumar, Kshitij Arun Doshi, Marcos E. Carranza
  • Publication number: 20230134683
    Abstract: Various approaches for configuring interleaving in a memory pool used in an edge computing arrangement, including with the use of infrastructure processing units (IPUs) and similar networked processing units, are disclosed. An example system may discover and map disaggregated memory resources at respective compute locations connected to each another via at least one interconnect. The system may identify workload requirements for use of the compute locations by respective workloads, for workloads provided by client devices to the compute locations. The system may determine an interleaving arrangement for a memory pool that fulfills the workload requirements, to use the interleaving arrangement to distribute data for the respective workloads among the disaggregated memory resources. The system may configure the memory pool for use by the client devices of the network, as the memory pool causes the disaggregated memory resources to host data based on the interleaving arrangement.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Inventors: Marcos E Carranza, Francesc Guim Bernat, Karthik Kumar, Kshitij Arun Doshi
  • Publication number: 20230132992
    Abstract: Various approaches for monitoring and responding to orchestration or service failures with the use of infrastructure processing units (IPUs) and similar networked processing units are disclosed. A method performed by a computing device for deploying remedial actions in failure scenarios of an orchestrated edge computing environment may include: identifying an orchestration configuration of a controller entity (responsible for orchestration) and a worker entity (subject to the orchestration to provide at least one service); determining a failure scenario of the orchestration of the worker entity, such as at a networked processing unit implemented at a network interface located between the controller entity and the worker entity; and causing a remedial action to resolve the failure scenario and modify the orchestration configuration, such as replacing functionality of the controller entity or the worker entity with functionality at a replacement entity.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Inventors: Francesc Guim Bernat, Christian Maciocco, Kshitij Arun Doshi, Karthik Kumar
  • Publication number: 20230136615
    Abstract: Various approaches for deploying and using virtual pools of compute resources with the use of infrastructure processing units (IPUs) and similar networked processing units are disclosed. A host computing system may be configured to operate a virtual pool of resources, with operations including: identifying, at the host computing system, availability of a resource at the host computing system; transmitting, to a network infrastructure device, a notification that the resource at the host computing system is available for use in a virtual resource pool in the edge computing network; receiving a request for the resource in the virtual resource pool that is provided on behalf of a client computing system, based on the request being coordinated via the network infrastructure device and includes at least one quality of service (QoS) requirement; and servicing the request for the resource, based on the at least one QoS requirement.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Inventors: Francesc Guim Bernat, Karthik Kumar, Marcos E. Carranza, Cesar Martinez-Spessot, Kshitij Arun Doshi