Patents by Inventor Katsuhiko Hieda
Katsuhiko Hieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6611017Abstract: A plurality of storage node electrodes are formed on a semiconductor substrate. A capacitor insulating film is formed on the storage node electrodes. A plate electrode, facing the storage node electrodes, is formed on the capacitor insulating film. A cavity is formed in the plate electrode.Type: GrantFiled: March 26, 2001Date of Patent: August 26, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Hieda
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Patent number: 6600166Abstract: Disclosed is a scanning exposure method, in which, when a pattern formed on a mask is transferred onto a wafer via an optical projection, the projecting region of the mask is limited by a slit, and the mask and the wafer are scanned in synchronism with the slit fixed so as to transfer the entire pattern region of the mask onto the wafer. In the scanning exposure method of the present invention, the exposure of the entire mask by the scanning of mask and the wafer is carried out twice by changing the exposure conditions. The first exposure and the second exposure are made opposite to each other in the scanning direction of the mask and the wafer so as to improve the pattern transfer accuracy.Type: GrantFiled: July 24, 2001Date of Patent: July 29, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Sato, Katsuhiko Hieda
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Publication number: 20030107076Abstract: A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric film; performing a thermal processing in a hydrogen-content atmosphere after the step of depositing the metal film; and patterning the metal film to form an upper electrode of the metal film after the step of performing the thermal processing. Thus, the adhesion between the upper electrode and the capacitor dielectric film is improved, and capacitor characteristics can be improved.Type: ApplicationFiled: June 19, 2002Publication date: June 12, 2003Applicants: Fujitsu Limited, Winbond Electronics Corp., Kabushiki Kaisha ToshibaInventors: Jun Lin, Chung-Ming Chu, Toshiya Suzuki, Katsuhiko Hieda
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Publication number: 20030107088Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.Type: ApplicationFiled: December 30, 2002Publication date: June 12, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Seiji Inumiya, Tomohiro Saito, Atsushi Yagishita, Katsuhiko Hieda, Toshihiko Iinuma
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Patent number: 6541813Abstract: The capacitor related to the present invention has a lower electrode, a dielectric film provided on the lower electrode and made mainly of crystal containing at Ti, O and at least one element selected from the group consisting of Ba and Sr, and an upper electrode provided on the dielectric film, wherein the dielectric film includes a layer which contacts the upper electrode. In case the dielectric film which has a thickness of at least 5 nm and exhibits a first-order differential spectrum measured by means of Auger electron spectroscopy, and the in the first-order differential spectrum, a ratio A/B is at most 0.3, where A is the absolute value A of a difference between a third peak appearing near 420 eV and a fourth peak appearing at a higher energy level and near the third peak, and B is the absolute value B of a difference between a first peak appearing near 410 eV and a third peak appearing at a lower energy level and near the first level.Type: GrantFiled: August 30, 2000Date of Patent: April 1, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Shoko Niwa, Hiroshi Tomita, Kazuhiro Eguchi, Katsuhiko Hieda
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Publication number: 20030047763Abstract: Disclosed is a semiconductor device comprising a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.Type: ApplicationFiled: October 10, 2002Publication date: March 13, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Kyoichi Suguro
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Patent number: 6515338Abstract: A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.Type: GrantFiled: March 23, 2000Date of Patent: February 4, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Tomohiro Saito, Atsushi Yagishita, Katsuhiko Hieda, Toshihiko Iinuma
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Publication number: 20030001290Abstract: A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a plurality of trenches, and these trenches have first and second bottoms that are different in depth. The semiconductor device comprises a plurality of cell transistors which include first diffusion layer regions formed in the first bottoms, which are shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to both the first and second diffusion layer regions and extend along at least one side-surface portions of the columnar portions.Type: ApplicationFiled: June 28, 2002Publication date: January 2, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Akihiro Nitayama, Katsuhiko Hieda
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Publication number: 20020190024Abstract: Presented is an etching method capable of easily etching an oxide containing an alkaline-earth metal. One method is to etch the oxide by using an etching gas containing a halogen gas except for fluorine, an interhalogen compound consisting of only a halogen element except for fluorine, or a halogen hydride consisting of a halogen element except for fluorine and hydrogen. Particularly chlorides, bromides, and iodides of alkaline-earth metals have relatively high vapor pressures, so a thin film containing an alkaline-earth metal can be etched by using chlorine gas, bromine gas, or iodine gas. When a halogen gas containing fluorine is used, damages to SiO2 portions used in a film formation apparatus are prevented by coating these SiO2 portions with a fluoride of an alkaline-earth metal.Type: ApplicationFiled: July 18, 2002Publication date: December 19, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Eguchi, Katsuya Okumura, Masahiro Kiyotoshi, Katsuhiko Hieda, Soichi Yamazaki
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Patent number: 6495054Abstract: Presented is an etching method capable of easily etching an oxide containing an alkaline-earth metal. One method is to etch the oxide by using an etching gas containing a halogen gas except for fluorine, an interhalogen compound consisting of only a halogen element except for fluorine, or a halogen hydride consisting of a halogen element except for fluorine and hydrogen. Particularly chlorides, bromides, and iodides of alkaline-earth metals have relatively high vapor pressures, so a thin film containing an alkaline-earth metal can be etched by using chlorine gas, bromine gas, or iodine gas. When a halogen gas containing fluorine is used, damages to SiO2 portions used in a film formation apparatus are prevented by coating these SiO2 portions with a fluoride of an alkaline-earth metal.Type: GrantFiled: October 29, 1999Date of Patent: December 17, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Eguchi, Katsuya Okumura, Masahiro Kiyotoshi, Katsuhiko Hieda, Soichi Yamazaki
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Patent number: 6482714Abstract: Disclosed is a semiconductor device comprising a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.Type: GrantFiled: February 24, 2000Date of Patent: November 19, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Kyoichi Suguro
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Publication number: 20020153552Abstract: A semiconductor device comprises a lower electrode shaped as a convex formed on a semiconductor substrate having crystals, a grain boundary between adjacent crystals being perpendicular to a side of the lower electrode, a capacitor insulating film covering the lower electrode, and an upper electrode formed on the capacitor insulating film.Type: ApplicationFiled: December 21, 1999Publication date: October 24, 2002Inventors: KATSUHIKO HIEDA, KAZUHIRO EGUCHI
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Publication number: 20020117698Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.Type: ApplicationFiled: April 26, 2002Publication date: August 29, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
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Patent number: 6403997Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.Type: GrantFiled: July 21, 2000Date of Patent: June 11, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
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Patent number: 6388282Abstract: A semiconductor memory device includes a transistor having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate, a bit line contact formed in an interlayer insulating film formed to cover the transistor and connected to one of the source and drain regions, a storage node electrode contact formed in the interlayer insulating film and connected to the other of the source and drain regions, a bit line contact plug formed on the bit line contact, a storage node electrode contact plug formed on the storage node electrode contact, a bit line formed to connect to the bit line contact plug, and a capacitor storage node electrode formed to connect to the storage node electrode contact plug.Type: GrantFiled: November 24, 2000Date of Patent: May 14, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Hieda
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Publication number: 20020048935Abstract: A semiconductor device includes a semiconductor substrate on which an element is formed, a lower wiring formed on the semiconductor substrate, and an upper wiring formed on and connected to the lower wiring. The upper wiring includes a plurality of regions having different thicknesses in a continuous wiring region excluding a connection region for connecting the upper and lower wirings.Type: ApplicationFiled: October 23, 2001Publication date: April 25, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuhiko Hieda
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Patent number: 6373085Abstract: A memory cell incorporated in a dynamic RAM is disclosed. The memory cell comprises a capacitor having a storage electrode formed in a trench, a first semiconductor layer formed on the capacitor, a connection member formed in the hole, a second semiconductor layer formed on the first semiconductor layer and the connection member, and a transistor formed in the second semiconductor layer. One of the source and the drain of the transistor is connected to the connection member in a direction of lamination of the substrate and the layers.Type: GrantFiled: December 21, 1998Date of Patent: April 16, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Hieda
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Patent number: 6351006Abstract: A semiconductor device comprises a semiconductor substrate and a capacitor provided above the semiconductor substrate and having an upper electrode, a lower electrode, and a dielectric film provided between the upper electrode and the lower electrode. At least one of the electrodes comprises an SrRuO3 film provided near the dielectric film and a conductive film made of conductive material other than SrRuO3 and provided far from the dielectric film.Type: GrantFiled: November 9, 1999Date of Patent: February 26, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Koji Yamakawa, Osamu Arisumi, Katsuhiko Hieda, Tsunetoshi Arikado, Hideyuki Kanai
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Publication number: 20020014600Abstract: Disclosed is a scanning exposure method, in which, when a pattern formed on a mask is transferred onto a wafer via an optical projection, the projecting region of the mask is limited by a slit, and the mask and the wafer are scanned in synchronism with the slit fixed so as to transfer the entire pattern region of the mask onto the wafer. In the scanning exposure method of the present invention, the exposure of the entire mask by the scanning of mask and the wafer is carried out twice by changing the exposure conditions. The first exposure and the second exposure are made opposite to each other in the scanning direction of the mask and the wafer so as to improve the pattern transfer accuracy.Type: ApplicationFiled: July 24, 2001Publication date: February 7, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Takashi Sato, Katsuhiko Hieda
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Publication number: 20020011612Abstract: A semiconductor device comprises a convex semiconductor layer provided on a semiconductor substrate, a source region and a drain region provided in the convex semiconductor layer, and a gate electrode. The gate electrode has a side-wall gate portion provided over a side surface of the convex semiconductor layer in an insulated state with respect to the convex semiconductor layer.Type: ApplicationFiled: July 30, 2001Publication date: January 31, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuhiko Hieda