Abstract: A semiconductor device with a charge holding capacitor comprises a lower electrode connected via a plug to one of the source and drain of an MIS transistor, a capacitor insulating film formed the lower electrode, an upper electrode formed on the capacitor insulating film. The lower electrode includes a first constituting portion that is embedded in a hole in which the plug has been embedded and so formed that it self-aligns with the plug and a second constituting portion which is formed on the first constituting portion and on regions outside the fist constituting portion and whose cross section is larger than that of the first constituting portion. The first constituting portion and the second constituting portion are formed integrally by a continues film.

Abstract: A semiconductor device includes a semiconductor substrate on which an element is formed, a lower wiring formed on the semiconductor substrate, and an upper wiring formed on and connected to the lower wiring. The upper wiring includes a plurality of regions having different thicknesses in a continuous wiring region excluding a connection region for connecting the upper and lower wirings.

Abstract: A plurality of storage node electrodes are formed on a semiconductor substrate. A capacitor insulating film is formed on the storage node electrodes. A plate electrode, facing the storage node electrodes, is formed on the capacitor insulating film. A cavity is formed in the plate electrode.

Abstract: A semiconductor device comprises a first lower capacitor electrode composed of a first conductive film, a second lower capacitor electrode composed of a second conductive film which covers at least the side face of the first lower capacitor electrode at its top face, a capacitor insulating film provided on the second lower capacitor electrode, and an upper capacitor electrode provided on the capacitor insulating film, wherein film stress in the first conductive film is lower than that in the second conductive film and the volume of the first conductive film is larger than that of the second conductive film. The above-described structure reduces leakage current in the capacitor.

Abstract: A p-type silicon substrate has an element isolation region of an STI structure formed therein. A transistor region isolated by the isolation region has a n-type source/drain diffusion layer. Further, a p-channel impurity layer is formed substantially only in its channel region for controlling its threshold voltage (Vth). A gate insulator film consisting of a high dielectric film is formed on the channel region with an Si3N4 film interposed therebetween. A metal gate electrode having its bottom and side surfaces covered with the gate insulator film is provided in a self-alignment manner with respect to the source/drain diffusion layer.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a position of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

Abstract: A solid raw material such as a powdery material is pressure-molded into a disk form to form a molded solid body. The molded solid body is heated to produce a source gas. The source gas is used in a film formation step in accordance with a chemical vapor deposition method. When the molded solid body is used, the source gas can be produced in an amount larger than the case where the powdery raw material is heated to obtain the source gas. In this case, an amount of carbon introduced into the film can be reduced compared to the case of using a liquefied material obtained by dissolving the raw material in a solvent. Furthermore, it is possible for a user to easily replace the raw material with a new one by using the molded solid body.

Abstract: A semiconductor memory device includes a semiconductor substrate and first, second, third and fourth spaced apart word lines formed on the semiconductor substrate and extending in a first direction. First, second, and third spaced apart bit lines are formed on the semiconductor substrate and extend in a second direction. An isolated active areas are formed on the semiconductor substrate under the second bit line. A first transfer gate transistor is formed in the active area, the first transfer gate transistor including spaced apart source and drain regions and the second word line being insulatively spaced from a channel region between the source and drain regions. A second transfer gate transistor is formed in the active area, the second transfer gate transistor including spaced apart source and drain regions and the third word line being insulatively spaced from a channel region between the source and drain regions.

Abstract: A shading film of chrome is formed entirely on one surface of a circular substrate of quartz. The substrate is rotated and resist is applied to the shading film. Since the substrate is shaped in a circle, the resist spreads uniformly on the entire surface of the shading film by the centrifugal force. Therefore, the resist has a substantially uniform film thickness over almost the entire surface of the shading film. This resist is patterned to form a resist pattern. By etching the shading film with the resist pattern used as a mask, a pattern preferable in accuracy of dimensions can be formed.

Abstract: A method of manufacturing a semiconductor device characterized by a method of forming a thin insulating film mainly composed of barium strontium titanate, the method having a first step for forming, on a semiconductor substrate, a thin BST film by a CVD method, and a second step for performing annealing at a temperature higher than a temperature at the thin BST films is formed so that crystallinity of the thin BST films is improved, wherein the temperature of the semiconductor substrate is maintained at a temperature higher than 250.degree. C. in a period of time between the first step and the second step in order to prevent a deterioration in a quality of the thin BST film.

Abstract: A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer.

Abstract: In the method of manufacturing a semiconductor device, according to the present invention, first, a dummy gate electrode consisting of a semiconductor layer and a non-metal cap layer formed on the semiconductor layer, is formed above a substrate. Then, diffusion layers are formed respectively on both sides of the dummy gate electrode. The dummy gate is used as a mask here, and thus the diffusion layers are self-aligned respectively with both sides of the dummy gate electrode. The formation of these diffusion layers requires a high-temperature heat treatment, however since the cap layer is made of a non-metal material, it is not melted down even in the high-temperature heat treatment. Next, the cap layer formed on the semiconductor layer is removed, and a gate groove made by the removal is filled with metal. Thus, a metal gate electrode made of a semiconductor layer and a metal layer is completed.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

Abstract: A semiconductor memory device comprises a matrix of memory cells, each having a transistor and a capacitor. A first electrode, a dielectric film and a second electrode are sequentially staked on a silicon monocrystalline substrate and epitaxially grown to form a capacitor having a multilayer structure. Then, an SOI layer is formed on the monocrystalline substrate carrying thereon the capacitor with an insulator film interposed therebetween. A source/drain diffusion layer is formed in the SOI layer and a gate electrode is formed to produce a MOS transistor. Either the source or the drain of the source/drain diffusion layer of the transistor is connected to the second electrode by way of the polysilicon layer in the contact hole running through the SOI layer and the insulator film layer.

Abstract: A dynamic RAM structure comprises a trench formed on a p-type Si substrate, a capacitor oxide film formed in such a manner as to cover an inner wall of the trench, a polysilicon film being a capacitor storage node electrode for burying the trench covered with the capacitor oxide film, an epitaxial Si layer formed on the Si substrate including an upper portion of the polysilicon film, a source/drain layer of a MOS transistor formed in the epitaxial Si layer, and a surface strap diffusion layer formed in the epitaxial Si layer in such a manner as to come in contact with the source/drain layer.

Abstract: A semiconductor memory device having a first memory cell and a second memory cell, includes a first semiconductor substrate having a first conductivity type, a first layer having a second conductivity type serving as a buried plate electrode, a first capacitor insulating film in the first memory cell, a second capacitor insulating film in the second memory cell, a second layer contacting the first capacitor insulating film having a second conductivity type serving as a memory node, a third layer contacting the second capacitor insulating film having a second conductivity type serving as a memory node, wherein an upper surface of the semiconductor substrate and an upper surface of the second layer and the third layer form a step height.

Abstract: A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

Abstract: A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

Abstract: Photolithographic alignment marks (e.g., mask and measurement overlay marks) are formed of a pattern of very small marks using the design configuration and rule of a circuit pattern feature. A relatively large mark comprising a pattern of small marks modeled after the circuit pattern feature results in an etch rate within the mark area that is substantially the same as the etch rate in the circuit pattern (e.g., cell or peripheral circuit) area. This allows for simultaneous formation of circuit pattern features, and the alignment marks, in a common etching step, while avoiding underetching (shallow etch depth) due to a microloading effect. In this manner, proper formation of readily detectible marks is ensured.

Abstract: A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.