Patents by Inventor Katsuhiko Hotta

Katsuhiko Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962142
    Abstract: The present disclosure includes: a power generator; and a power line through which power generated by the power generator is transmitted to a load. The power line between the power generator and the load is provided with: a current limitation device configured to, when detecting occurrence of a fault current, limit the fault current; and a current interruption device configured to interrupt current heading for the load, in conjunction with the limitation of the fault current performed by the current limitation device.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 16, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Katsuhiko Horinouchi, Katsuki Hotta, Tsuguhiro Takuno
  • Publication number: 20230187275
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: February 3, 2023
    Publication date: June 15, 2023
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 11600522
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: March 7, 2023
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20210296165
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 23, 2021
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 11062938
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20200411370
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 10796953
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 6, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20200211897
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 10600683
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 24, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 10332795
    Abstract: It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyoshi Maeshima, Kotaro Horikoshi, Katsuhiko Hotta, Toshiyuki Takahashi, Hironori Ochi, Kenichi Shoji
  • Publication number: 20190088537
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: October 24, 2018
    Publication date: March 21, 2019
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 10141257
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 9899316
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20170358489
    Abstract: It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.
    Type: Application
    Filed: August 7, 2017
    Publication date: December 14, 2017
    Inventors: Kiyoshi MAESHIMA, Kotaro HORIKOSHI, Katsuhiko HOTTA, Toshiyuki TAKAHASHI, Hironori OCHI, Kenichi SHOJI
  • Publication number: 20170271259
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: June 7, 2017
    Publication date: September 21, 2017
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 9761487
    Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyoshi Maeshima, Kotaro Horikoshi, Katsuhiko Hotta, Toshiyuki Takahashi, Hironori Ochi, Kenichi Shoji
  • Patent number: 9536821
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
  • Publication number: 20160365278
    Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.
    Type: Application
    Filed: May 5, 2016
    Publication date: December 15, 2016
    Inventors: Kiyoshi MAESHIMA, Kotaro HORIKOSHI, Katsuhiko HOTTA, Toshiyuki TAKAHASHI, Hironori OCHI, Kenichi SHOJI
  • Publication number: 20160358853
    Abstract: A semiconductor device includes a silicon nitride film formed above a front surface side of a semiconductor substrate, a first wiring formed above the silicon nitride film, a second wiring containing aluminum formed over the first wiring via a first insulating film, a second insulating film having an opening over the second wiring, and aluminum nitride formed over the second wiring at a bottom surface of the opening.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Inventors: Ayaka OKUMURA, Katsuhiko HOTTA, Yoshinori KONDO, Hiroaki OSAKA
  • Publication number: 20160293542
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 6, 2016
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA