Patents by Inventor Katsuhiko Hotta

Katsuhiko Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9443817
    Abstract: Characteristics of a semiconductor device are improved. An opening that exposes a pad region of a top-layer wiring containing aluminum is formed in a protection film over the wiring, and aluminum nitride is formed on a surface of the exposed wiring. Additionally, a silicon nitride film is formed on a back surface of a semiconductor substrate having the wiring. As described above, foreign substances generated over the pad region due to the silicon nitride film on the back surface of the semiconductor substrate can be prevented by providing an aluminum nitride film over the pad region. Particularly, even in a case of requiring time before an inspection step and a bonding step, after a formation step of the pad region, formation reaction of the foreign substances can be prevented in the pad region, and the characteristics of the semiconductor device can be improved.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: September 13, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Ayaka Okumura, Katsuhiko Hotta, Yoshinori Kondo, Hiroaki Osaka
  • Patent number: 9391022
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: July 12, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20150228579
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: April 24, 2015
    Publication date: August 13, 2015
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Publication number: 20150200158
    Abstract: Characteristics of a semiconductor device are improved. An opening that exposes a pad region of a top-layer wiring containing aluminum is formed in a protection film over the wiring, and aluminum nitride is formed on a surface of the exposed wiring. Additionally, a silicon nitride film is formed on a back surface of a semiconductor substrate having the wiring. As described above, foreign substances generated over the pad region due to the silicon nitride film on the back surface of the semiconductor substrate can be prevented by providing an aluminum nitride film over the pad region. Particularly, even in a case of requiring time before an inspection step and a bonding step, after a formation step of the pad region, formation reaction of the foreign substances can be prevented in the pad region, and the characteristics of the semiconductor device can be improved.
    Type: Application
    Filed: January 8, 2015
    Publication date: July 16, 2015
    Inventors: Ayaka OKUMURA, Katsuhiko HOTTA, Yoshinori KONDO, Hiroaki OSAKA
  • Publication number: 20150194381
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Application
    Filed: March 24, 2015
    Publication date: July 9, 2015
    Inventors: Takuro HOMMA, Katsuhiko HOTTA, Takashi MORIYAMA
  • Patent number: 9048200
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 2, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
  • Publication number: 20140199831
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: March 16, 2014
    Publication date: July 17, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 8704373
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 8686538
    Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
  • Publication number: 20140038409
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: October 1, 2013
    Publication date: February 6, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Patent number: 8581415
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 8518821
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: August 27, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 8513808
    Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
  • Patent number: 8487412
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20130065330
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 14, 2013
    Inventors: TAKURO HOMMA, Katsuhiko Hotta, Takashi Moriyama
  • Patent number: 8373270
    Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
  • Patent number: 8350311
    Abstract: The present invention provides a technology capable of providing a semiconductor device having an MIM structure capacitor with improved reliability. The capacitor has a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is comprised of a metal film embedded in an electrode groove formed in an insulating film over the main surface of a semiconductor substrate; and the upper electrode is comprised of a film stack of a TiN film (lower metal film) and a Ti film (cap metal film) formed over the TiN film (lower metal film).
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kaneko, Hiroyasu Noso, Katsuhiko Hotta, Shinichi Ishida, Hidenori Suzuki, Sadayoshi Tateishi
  • Publication number: 20120319235
    Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
    Type: Application
    Filed: August 28, 2012
    Publication date: December 20, 2012
    Inventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
  • Publication number: 20120248613
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: June 15, 2012
    Publication date: October 4, 2012
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20120252205
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: June 15, 2012
    Publication date: October 4, 2012
    Inventors: Katsuhiko Hotta, Kyoko Sasahara