Patents by Inventor Katsuhiko Hotta
Katsuhiko Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8269309Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.Type: GrantFiled: March 25, 2011Date of Patent: September 18, 2012Assignee: Renesas Electronics CorporationInventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
-
Patent number: 8158266Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using a SiOC film as an interlayer film. In the invention, by forming an interlayer film from a SiOC film having a Si—CH3 bond/Si—O bond ratio less than 2.50% or having a strength ratio determined by the FT-IR of a Si—OH bond to a SiO—O bond exceeding 0.0007, a strength ratio of a SiH bond to a SiO—O bond at a wavelength of 2230 cm?1 exceeding 0.0050 and a strength ratio of a Si—H bond to a SiO—O bond at a wavelength of 2170 cm?1 exceeding 0.0067, the interlayer film has a relative dielectric constant of to 3 or less, and owing to suppression of lowering in hardness or elastic modulus, has improved mechanical strength.Type: GrantFiled: May 17, 2010Date of Patent: April 17, 2012Assignee: Renesas Electronics CorporationInventors: Masami Takayasu, Katsuhiko Hotta
-
Publication number: 20110266679Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.Type: ApplicationFiled: April 27, 2011Publication date: November 3, 2011Inventors: Katsuhiko Hotta, Takeshi Furusawa, Toshikazu Matsui, Takuro Homma
-
Publication number: 20110183513Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
-
Patent number: 7986041Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductor layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: June 15, 2010Date of Patent: July 26, 2011Assignee: Renesas Electronics CorporationInventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
-
Publication number: 20110169128Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.Type: ApplicationFiled: March 25, 2011Publication date: July 14, 2011Inventors: KATSUHIKO HOTTA, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
-
Publication number: 20110156208Abstract: The present invention provides a technology capable of providing a semiconductor device having an MIM structure capacitor with improved reliability. The capacitor has a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is comprised of a metal film embedded in an electrode groove formed in an insulating film over the main surface of a semiconductor substrate; and the upper electrode is comprised of a film stack of a TiN film (lower metal film) and a Ti film (cap metal film) formed over the TiN film (lower metal film).Type: ApplicationFiled: December 22, 2010Publication date: June 30, 2011Inventors: Yoshiyuki KANEKO, Hiroyasu Noso, Katsuhiko Hotta, Shinichi Ishida, Hidenori Suzuki, Sadayoshi Tateishi
-
Patent number: 7968966Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.Type: GrantFiled: September 21, 2009Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
-
Patent number: 7932606Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.Type: GrantFiled: February 14, 2008Date of Patent: April 26, 2011Assignee: Renesas Electronics CorporationInventors: Katsuhiko Hotta, Kyoko Sasahara
-
Publication number: 20100264414Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film.Type: ApplicationFiled: April 15, 2010Publication date: October 21, 2010Inventors: Takuro HOMMA, Katsuhiko Hotta, Takashi Moriyama
-
Publication number: 20100252933Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductor layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: ApplicationFiled: June 15, 2010Publication date: October 7, 2010Applicant: RENESAS TECHNOLOGY CORPORATIONInventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
-
Publication number: 20100221913Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using a SiOC film as an interlayer film. In the invention, by forming an interlayer film from a SiOC film having a Si—CH3 bond/Si—O bond ratio less than 2.50% or having a strength ratio determined by the FT-IR of a Si—OH bond to a SiO—O bond exceeding 0.0007, a strength ratio of a SiH bond to a SiO—O bond at a wavelength of 2230 cm?1 exceeding 0.0050 and a strength ratio of a Si—H bond to a SiO—O bond at a wavelength of 2170 cm?1 exceeding 0.0067, the interlayer film has a relative dielectric constant of to 3 or less, and owing to suppression of lowering in hardness or elastic modulus, has improved mechanical strength.Type: ApplicationFiled: May 17, 2010Publication date: September 2, 2010Inventors: Masami TAKAYASU, Katsuhiko Hotta
-
Patent number: 7772700Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: August 26, 2005Date of Patent: August 10, 2010Assignee: Renesas Technology Corp.Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
-
Publication number: 20100193958Abstract: A technique is provided for improving the security of information stored in a semiconductor device. Multilayer wiring layers are formed over a semiconductor substrate. Wirings are formed on the uppermost wiring layer among those multilayer wiring layers. On the wirings, there is formed, in the following order, a silicon oxide film, a colored thin film, and a silicon oxide film, over which, a silicon nitride film serving as a surface protective film is formed. In other words, the invention is characterized by that the colored thin film is formed between the wiring constituting the uppermost wiring layer and the silicon nitride film serving as the surface protective film. The colored thin film has a function of attenuating visible light and laser light in the specific wavelength region, and is formed of, for example, a silicon oxide film containing cobalt oxide.Type: ApplicationFiled: April 15, 2010Publication date: August 5, 2010Inventors: Kozo WATANABE, Michimoto KAMINAGA, Katsuhiko HOTTA
-
Patent number: 7718269Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using a SiOC film as an interlayer film. In the invention, by forming an interlayer film from a SiOC film having a Si—CH3 bond/Si—O bond ratio less than 2.50% or having a strength ratio determined by the FT-IR of a Si—OH bond to a SiO—O bond exceeding 0.0007, a strength ratio of a SiH bond to a SiO—O bond at a wavelength of 2230 cm?1 exceeding 0.0050 and a strength ratio of a Si—H bond to a SiO—O bond at a wavelength of 2170 cm?1 exceeding 0.0067, the interlayer film has a relative dielectric constant of to 3 or less, and owing to suppression of lowering in hardness or elastic modulus, has improved mechanical strength.Type: GrantFiled: March 14, 2006Date of Patent: May 18, 2010Assignee: Renesas Technology Corp.Inventors: Masami Takayasu, Katsuhiko Hotta
-
Patent number: 7705462Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: GrantFiled: September 21, 2009Date of Patent: April 27, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
-
Publication number: 20100013046Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.Type: ApplicationFiled: September 21, 2009Publication date: January 21, 2010Inventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
-
Publication number: 20100007024Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: ApplicationFiled: September 21, 2009Publication date: January 14, 2010Inventors: Ken UCHIKOSHI, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masahi Sahara, Kazuhiko Sato
-
Patent number: 7629251Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.Type: GrantFiled: June 18, 2008Date of Patent: December 8, 2009Assignee: Renesas Technology Corp.Inventors: Katsuhiko Hotta, Kyoko Sasahara
-
Patent number: 7615848Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: GrantFiled: June 12, 2008Date of Patent: November 10, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato