Patents by Inventor Katsuhiko Hotta

Katsuhiko Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7602040
    Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
  • Patent number: 7557034
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: July 7, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20080286964
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: June 18, 2008
    Publication date: November 20, 2008
    Inventors: Katsuhiko HOTTA, Kyoko Sasahara
  • Publication number: 20080277794
    Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.
    Type: Application
    Filed: June 12, 2008
    Publication date: November 13, 2008
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Publication number: 20080254616
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: June 18, 2008
    Publication date: October 16, 2008
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Publication number: 20080211108
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: February 14, 2008
    Publication date: September 4, 2008
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20080211103
    Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
    Type: Application
    Filed: April 14, 2008
    Publication date: September 4, 2008
    Inventors: Katsuhiko HOTTA, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
  • Patent number: 7419901
    Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: September 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
  • Patent number: 7400046
    Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: July 15, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Patent number: 7372154
    Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
  • Patent number: 7354855
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: April 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 7303986
    Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge to be suppressed to a low level, and the short-circuiting-failure between adjacent wirings to be suppressed or prevented.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 4, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Publication number: 20070228574
    Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.
    Type: Application
    Filed: May 31, 2007
    Publication date: October 4, 2007
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Publication number: 20070222043
    Abstract: A technique is provided for improving the security of information stored in a semiconductor device. Multilayer wiring layers are formed over a semiconductor substrate. Wirings are formed on the uppermost wiring layer among those multilayer wiring layers. On the wirings, there is formed, in the following order, a silicon oxide film, a colored thin film, and a silicon oxide film, over which, a silicon nitride film serving as a surface protective film is formed. In other words, the invention is characterized by that the colored thin film is formed between the wiring constituting the uppermost wiring layer and the silicon nitride film serving as the surface protective film. The colored thin film has a function of attenuating visible light and laser light in the specific wavelength region, and is formed of, for example, a silicon oxide film containing cobalt oxide.
    Type: Application
    Filed: February 12, 2007
    Publication date: September 27, 2007
    Inventors: Kozo Watanabe, Michimoto Kaminaga, Katsuhiko Hotta
  • Patent number: 7247525
    Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: July 24, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
  • Publication number: 20070114631
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: January 16, 2007
    Publication date: May 24, 2007
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Patent number: 7208391
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: April 24, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Publication number: 20070066050
    Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge to be suppressed to a low level, and the short-circuiting-failure between adjacent wirings to be suppressed or prevented.
    Type: Application
    Filed: November 21, 2006
    Publication date: March 22, 2007
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Patent number: 7189637
    Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge can be suppressed to a low level, and the short-circuiting failure between adjacent wirings can be suppressed or prevented.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: March 13, 2007
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Publication number: 20070026664
    Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
    Type: Application
    Filed: June 16, 2006
    Publication date: February 1, 2007
    Inventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano