Abstract: A multiplier circuit includes first and second squaring circuits each having a differential input terminal pair. A first input terminal of the differential input terminal pair of the first squaring circuit is applied with a first input voltage and the second input terminal thereof is applied with a second input voltage opposite in phase to the first input voltage. A first input terminal of the differential input terminal pair of the second squaring circuit is supplied with the second input voltage and the second input terminal thereof is applied with the first input voltage. The first and second squaring circuits each includes two sets of unbalanced differential transistor pairs which are arranged so that their inputs are opposite in phase and their outputs are connected in common. The transistors of each unbalanced differential transistor pair have different emitter sizes.

Abstract: M1 and M2, because their capacity ratio is 1:K.sub.1, have different gate-source voltages. M3 and M4, which constitute a current mirror circuit, have a capacity ratio of K.sub.2 :1. Thus, M1 and M2 are driven at a current ratio of K.sub.2 :1. As a result, the temperature dependence of mobility and that of threshold voltage can cancel each other to make it possible to realize on a CMOS integrated circuit a reference voltage generating circuit with reduced temperature dependence. As the output reference voltage, V.sub.REF will be used if a resistor R1 is present, or V.sub.REF will be used if the resistor R1 is dispensed with. The output may as well be taken out of the gate of M2 (V.sub.REF2), or out of the drain of M2 in which case the drain is provided with a resistor. Q1 and Q2, which are PNP transistors, have an emitter size ratio (Q1:Q2) of 1:K.sub.1, and their bases are commonly connected and grounded via an analog ground V.sub.AG, their collectors being also grounded. Thus Q1 and Q2 are diode-connected.

Abstract: A frequency multiplier and mixer circuit comprises a frequency multiplier circuit composed of a first differential amplifier, which includes a first differential circuit formed of source-coupled first and second FETs having their sources connected in common to a first constant current source and a second differential circuit formed of source-coupled third and fourth FETs having their sources connected in common to a second constant current source. The first and second differential circuits constitute two identical unbalanced source-coupled pairs having the same gate width/length ratio K, input terminals of the pairs being connected in cross-coupled fashion, the output terminals of the pairs being connected in parallel. Gates of the first and third FETs are connected in common to one terminal of a first pair of input terminals for receiving a signal to be frequency-multiplied, and gates of the second and fourth FETs are connected in common to the other terminal of the first pair of input terminals.

Abstract: A differential amplifier circuit including a quadritail circuit and a differential pair of transistors. The quadritail circuit has a first pair of first and second MOS transistors, a second pair of third and fourth MOS transistors, and a constant current source for driving the first and second pairs. The differential pair is composed of fifth and sixth MOS transistors and driven by an output current of the quadritail circuit. An input voltage is applied between the gates of the first and second transistors and between the gates of the fifth and sixth transistors. A DC voltage is applied to the common-connected gates of the third and fourth transistors. An output current is derived from an output end of the differential pair. The transconductance linearity of the differential amplifier circuit can be improved.

Abstract: A constant voltage circuit formed of MOS transistors is provided, which comprises a reference voltage generator and an error amplifier performing the temperature compensation of a reference voltage outputted from the reference voltage generator and outputting a constant voltage. The reference voltage generator comprises first, second and third MOS transistors each driven by a constant current source, and outputs the reference voltage to the connecting end with the error amplifier. The error amplifier includes a differential pair of fourth and fifth MOS transistors whose capacity ratio is 1:K1, and an active load composed of sixth and seventh transistors whose capacity ratio is 1:K2. One of input pair of the differential pair is applied with the reference voltage and the other thereof is applied with a voltage obtained by dividing the constant voltage.

Abstract: A temperature sensor circuit with a differential output, a differential pair circuit and a feedback circuit. The differential pair circuit has a first MOS transistor whose gate is connected to an output terminal of the temperature sensor circuit and to a reference voltage and a second MOS transistor whose source is connected to the source of the first MOS transistor. The capacity ratios, or gate-width and gate-length ratios (W/L) of the first and second MOS transistors are different. The first and second MOS transistors have a load circuit connected to their drains and a constant current source connected to their sources. The output voltage of the differential pair circuit is connected to the other output terminal of the temperature sensor circuit, as well as to the gate of the second MOS transistor thereby feedback-controlling the differential pair circuit so that the drain currents of the first and second MOS translators are equal to each other.

Abstract: In a logarithmic amplifier circuit including a plurality of cascaded differential amplifiers, a plurality of blocks of logarithmic full-wave rectifiers are provided, each producing output currents having logarithmic full-wave rectification characteristics in respect to voltages of their input signals. Each logarithmic full-wave rectifier is formed by a plurality of squaring full-wave rectifiers each producing an intermediate current having squaring full-wave characteristics. A current adder is provided for each or a group of the squaring full-wave rectifiers to add up the intermediate currents thereof and produce an output current. A common adder is provided for adding the output currents from all logarithmic full-wave rectifiers to produce a current output signal.

Abstract: Disclosed is a frequency doubling and mixing circuit capable of effecting frequency doubling operation and mixing operation with one unit of circuit. It includes a first set of differential transistor-pair which have emitters connected in common and an emitter size ratio of K:1 (K is larger than 1), and a second set of differential transistor-pair which similarly have emitters connected in common and an emitter size ratio of K:1. These two sets of differential transistor-pairs have respective constant electric currents supplied. In addition, it has a differential amplifying circuit which is driven by a differential current between the common collector output of one transistor of the first set of differential transistor-pair and one transistor of the second set of differential transistor-pair and the common collector output between the other transistor of the first set of differential transistor-pair and the other transistor of the second set of differential transistor-pair.

Abstract: An operational circuit without using a clock signal to be used for a compressing or expanding circuit, which comprises a first and second DC signals different in polarity from each other are obtained in response to an input AC signal. The AC signal and a first DC signal are differentially amplified to obtain a first differential output signal, and the AC signal and a second DC signal are differentially amplified to obtain a second differential output signal. A rectified AC signal thus obtained is averaged to obtain an averaged rectified signal as well as to obtain a first and second signals in accordance with the averaged rectified signal. The AC signal and the first signal are differentially amplified to obtain a third differential output signal and the AC signal and the second signal are differentially amplified to obtain a fourth differential output signal.

Abstract: A frequency mixer circuit having a differential pair composed of first and second field effect transistors (FET) whose performance characteristics, or transconductance parameters, are different from each other and whose sources are connected in common. The both FETs are driven with a constant current. An RF signal is applied to the gate of the first FET and a local oscillator signal is applied to the gate of the second FET. An output signal is taken out by converting the drain current of the first or second FET into a voltage. Such a drain current that has a square characteristic can be obtained in each of the first and second FETs, so that even if the local oscillator signal level is lower than that of several volts, the circuit can be operated without raising any problem.

Abstract: A rectifier circuit without using a clock signal is provided. In this circuit, a polarity judgment circuit receives an AC signal and judges the positive/negative polarity of voltage of the AC signal and output the polarity specification signal. A gain control circuit receives the polarity specification signal and outputs a first and a second gain control signals having different DC voltage differences between the times when the result of "Positive polarity" is shown and when the result of "Negative polarity" is shown. A first amplifier circuit amplifies the AC signal differentially, and a second amplifier circuit amplifies the AC signal thus amplified differentially again while gain controlled according to the first and second gain control signals. A rectified signal is outputted from differential output terminals of the second amplifier circuit.

Abstract: A frequency discriminator is provided which comprises a phase shifter for shifting a phase of an IF signal, a multiplier for analogically multiplying the IF signal and an output signal of the phase shifter and outputting the resultant signal thus obtained as a differential current, a circuit for forming a differential current of a differential output current of the multiplier, an inverter circuit to be driven by the differential current thus formed, and a low-pass filter for integrating an output signal of the inverter circuit. As the circuit for forming the differential current thereof, a current mirror circuit is preferably used. Thus, a quadrature-type frequency discriminator can be realized on a C-MOS integrated circuit.

Abstract: A frequency mixing circuit is provided which comprises first and second differential pairs each formed of two transistors different in emitter area from each other and constant current sources for respectively driving the first and second differential pairs. The collectors of the transistors having a large emitter area of K (K>1) and the collectors of the transistors having a small emitter area of 1 of the first and second differential pairs are respectively connected in common. Between the both differential pairs, the bases of the transistors having a emitter area of K and the bases of the transistors having a emitter area of 1 are respectively connected in common. A first AC signal to be mixed is applied to one of two sets of the commonly connected bases and a second AC signal to be mixed is applied to the other thereof. Thus, the degradation of NF can be reduced and a good high frequency characteristic can be obtained at a low current.

Abstract: A four quadrant analog multiplier circuit including first to third squaring circuits 1 to 3 each of which is composed of first and second differential circuits each of which is formed of first and second metal-oxide semiconductor (MOS) transistors M.sub.1 and M.sub.2, M.sub.3 and M.sub.4, M.sub.5 and M.sub.6, M.sub.7 and M.sub.8, M.sub.9 and M.sub.10, and M.sub.11 and M.sub.12. A gate width-to-length ratio W.sub.2 /L.sub.2 of the second MOS transistor M.sub.2 is larger than a gate width-to-length ratio W.sub.1 /L.sub.1 of the first MOS transistor M.sub.1. A gate of the first MOS transistor M.sub.1, M.sub.5 and M.sub.9 of each first differential circuit is connected to a gate of the second MOS transistor M.sub.4, M.sub.8 and M.sub.12 of the corresponding second differential circuit. A gate of the second MOS transistor M.sub.2, M.sub.6 and M.sub.10 of each first differential circuit is connected to a gate of the first MOS transistor M.sub.3, M.sub.7 and M.sub.11 of the corresponding second differential circuit.

Abstract: A multiplier comprises first and second squaring circuits each including first and second MOS transistors having their sources connected in common and third and fourth MOS transistors having their sources connected in common. The first and third transistors have a first gate W/L ratio and have their drains connected to each other, and the second and fourth transistors have their drains connected to each other and have a second gate W/L ratio different from the first ratio. Gates of the first and fourth transistors are connected to each other, and gates of the second and third transistors are connected to each other. A first input signal is supplied to the gates of the first and fourth transistors of each of the first and second squaring circuits, and a second input signal is supplied, without being inverted, to the gates of the second and third transistors of the first squaring circuit, and without being inverted, to the gates of the second and third transistors of the second squaring circuit.

Abstract: A logarithmic amplifier circuit has n (n>1) stages of differential amplifiers, n+1 in number, of rectifying circuits, a differential pair of bipolar transistors having different emitter sizes in the ratio of 1/J (J>1) and a differential pair of MOS transistors of which the ratio of a gate-width and a gate-length W/L is 1/K (K>1). The bipolar transistors and the MOS transistors form an output pair. A collector of one of the bipolar transistors having a larger emitter size and a drain of one of MOS transistors having a larger W/L ratio are connected together, and a collector of the other of bipolar transistors having a smaller emitter size and a drain of the other of MOS transistors having a smaller W/L ratio are connected together. A subtraction circuit outputs a difference in the currents flowing in each of the output pair and outputs from all the subtraction circuits are added up at a common load resistor.

Abstract: In an intermediate frequency amplification circuit comprising first through n-th differential amplifiers which are connected in cascade to one another with the first amplifier supplied with a circuit input signal and which successively produce amplifier output signals with an n-th amplifier output signal produced as a circuit output signal from the n-th amplifier, first through (n+1)-th rectification circuits are supplied with respective amplifier output signals with the circuit input signal given to the first rectification circuit. Each rectification circuit comprises a differential unit comprising at least one pair of transistors which have different emitter areas from each other to rectify each amplifier output signal and to produce a collector current which is summed up by an adder circuit to be produced as a field strength signal. The rectification circuits may carry out either half-wave rectification or full-wave rectification.

Abstract: A battery-powered radio communication apparatus is disclosed which comprises a power amplifier and a power detector for detecting the output power of the power amplifier. A supply voltage detector compares a standard voltage with the output voltage of a battery supplying power to the power amplifier. A gain control circuit controls the gain of the power amplifier in response to the output of the power amplifier and to the output of the supply voltage detector so as to prolong, by a certain time, the communicable state of the apparatus prior to battery depletion.

Abstract: An intermediate frequency amplifier stage is disclosed, in which linearity of a signal strength detection output is improved. The intermediate frequency amplifier stage includes a plurality of intermediate frequency amplifiers, a plurality of double-wave rectifiers each coupled to the associated intermediate frequency amplifier and making full-wave rectification of the signal supplied from the associated intermediate frequency amplifier, and an adder circuit adding the rectification outputs of the respective double-wave rectifiers.

Abstract: In a portable radio communication apparatus comprising a handset (20) having a side surface (23) and a recessed surface (24), first and second antennae (51 and 52) of different resonance frequencies are fixed to the recessed surface by first and second conductive plates (55 and 56), respectively. First and second conductive lines (61 and 62) connect a common conductive line (63) to the first and the second antennae, respectively. The common conductive line is connected to an electro-audio and audio-electro converting device (30) to feed a transmitting electric signal to the first and the second antennae and to receive the received electric signal from the first and second antennae. The first and the second antennae have first and second antenna widths (W.sub.1 and W.sub.2), respectively. The first and the second conductive plates have first and second plate widths, respectively, and first and second axes centrally of the first and the second plate widths, respectively.