Abstract: A MOS differential amplifier circuit has a differential pair having first and second MOS transistors. The source electrodes of the first and second MOS transistors are commonly coupled and driven by a constant current source. The current sources can be controlled so that the difference between the common mode voltage and the common source voltage becomes constant, and a level shifter may be provided for level-shifting the common source voltage of the first and second MOS transistor. The MOS differential amplifier circuit so designed can be used in a voltage adder/subtractor circuit.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ′ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ′ of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ/2 of the current mirror circuit 2 determine the differential output current I′.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ−/2 of the current mirror circuit 2 determine the differential output current I+.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ−/2 of the current mirror circuit 2 determine the differential output current I+.

Abstract: A flicker correction apparatus for correcting a flicker component of an image signal obtained by imaging an object using an imaging device is provided. The apparatus comprises an image average calculation section for calculating an average of the image signal, a flicker frequency calculation section for calculating a flicker frequency, a flicker data extraction section for extracting flicker data using the average of the image signal and the flicker frequency, a flicker determination section for determining the presence or absence of a flicker phenomenon using the flicker data, a flicker correction amount calculation section for calculating a flicker correction amount using the flicker data, and a flicker correction section for removing the flicker component of the image data using the flicker correction amount.

Abstract: In a quadrature mixer circuit for receiving a radio frequency signal to generate first and second quadrature output signals, a first three-input mixer receives the radio frequency signal, a first local signal having a first frequency and a second local signal having a second frequency to generate the first quadrature output signal, and a second three-input mixer receives the radio frequency signal, the first local signal and the second local signal to generate the second quadrature output signal. The second local signal received by the first three-input mixer and the second local signal received by the second three-input mixer being out of phase by &pgr;/2 from each other.

Abstract: A variable gain amplifier circuit (100) that may have a gain exponentially changed has been disclosed. A variable gain amplifier circuit (100) may include a first OTA (Operational Transconductance Amplifier) (11) and a second OTA (12). A first OTA (11) may receive a differential voltage at input terminals (IN1 and IN2). A second OTA (12) may receive an output from a first OTA (11) and may provide a differential output voltage at output terminals (OUT1 and OUT2). A second OTA (12) may have second OTA input terminals and second OTA output terminals commonly connected to output terminals (OUT1 and OUT2). A small-signal transconductance of the first and second OTAs (11 and 12) may be proportional to driving currents. A first OTA (11) may have a driving current of I0{1+tan h(x/a)} and a second OTA (12) may have a driving current of I0{1−tan h(x/a)}, where −1<x<1 and a is a constant.

Abstract: A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: There is disclosed a reference current circuit capable of preventing an appearance of the effect of the Early voltage, operated from a low power supply voltage, and adapted to output a current having a positive or optional temperature characteristic. In this reference current circuit, by a self-biased method, a current of a current mirror circuit is set to be proportional or substantially inversely proportional to a temperature by first and second transistors constituting a non-linear current mirror circuit. A third transistor is provided. A current of the third transistor proportional to a third voltage between a control terminal and a current input terminal is set to be substantially inversely proportional to the temperature, and the currents of the current mirror circuit and the third transistor are weighted and added. Thus, an output current having a fixed temperature current is obtained.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ/2 of the current mirror circuit 2 determine the differential output current I+.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ−/2 of the current mirror circuit 2 determine the differential output current I+.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ−/2 of the current mirror circuit 2 determine the differential output current I+.

Abstract: A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent characteristic, comprises first and second diode-connected transistors (or diodes), respectively grounded and driven with two constant currents bearing a constant current ratio to each other, and a unit for amplifying a differential voltage of output voltages from the first and second transistors by a preset factor and for summing the amplified differential voltage to an output voltage of the first or second transistor. The amplifying and summing unit is formed by two OTAs 11, 12 and a current mirror circuit 13.

Abstract: A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: There is disclosed a reference current circuit capable of preventing an appearance of the effect of the Early voltage, operated from a low power supply voltage, and adapted to output a current having a positive or optional temperature characteristic. In this reference current circuit, by a self-biased method, a current of a current mirror circuit is set to be proportional or substantially inversely proportional to a temperature by first and second transistors constituting a non-linear current mirror circuit. A third transistor is provided. A current of the third transistor proportional to a third voltage between a control terminal and a current input terminal is set to be substantially inversely proportional to the temperature, and the currents of the current mirror circuit and the third transistor are weighted and added. Thus, an output current having a fixed temperature current is obtained.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ−/2 of the current mirror circuit 2 determine the differential output current I+.

Abstract: A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: To provide a linear transconductance amplifier which is easily implemented with LSI and has a linear transconductance superior in a frequency characteristic. In a MOS linear transconductance amplifier according to the present invention, gates of transistors M1 and M2 whose sources are grounded form an input pair, to which a differential voltage is inputted, the gate and drain of a transistor M3 are mutually connected, and drains of the transistors M1, M2 and M3 are mutually connected and are driven by a constant current. The MOS linear transconductance amplifier includes a unit for adding a current flowing in the transistor M1 to a current that is a half of a current flowing in the transistor M3, and a unit for adding a current flowing in the transistor M2, and a current that is a half of a current flowing in the transistor M3, and these two sum currents are made to be differential output current.

Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 21. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ−/2 of the current mirror circuit 2 determine the differential output current I+.

Abstract: An OTA capable of completely linear operation within the entire operable input range is provided. This OTA includes a differential pair of first and second bipolar transistors, a first current source/sink for driving the first transistor, a second current source/sink for driving the second transistor, and a resistor connected to an emitter of the first transistor and an emitter of the second transistor. The emitters of the first and second transistors are coupled together through the resistor. The differential pair has a pair of input terminals of the OTA. A first current mirror having an input terminal and an output terminal and a second current mirror having an input terminal and an output terminal are provided. The input terminal of the first current mirror is connected to the first transistor. The input terminal of the second current mirror is connected to the second transistor.