Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.

Abstract: A multiplier core circuit using four transistors, in which a novel input voltage combination is adopted. This circuit contains first, second, third and fourth bipolar transistors or field-effect transistors whose emitters or sources are coupled together. Collectors or drains of the first and second transistors are coupled together to form an output end and collectors or drains of the third and fourth transistors are coupled together to form the other output end. An output signal of the circuit is differentially taken out from the output ends. The first to fourth transistors are applied with first to fourth voltages at their base or gate. The first, second, third and fourth voltages are ?-V.sub.x +(1/2)V.sub.y !, (V.sub.x +V.sub.y), (-V.sub.x +V.sub.y) and ?V.sub.x +(1/2)V.sub.y !, respectively. These four voltages may be (V.sub.x -V.sub.y), 2V.sub.x, V.sub.x and (2V.sub.x -V.sub.y), respectively. If a, b and c are positive constants, these four voltages may be expressed as (aV.sub.x +bV.sub.y), ?(a-c)V.sub.

Abstract: A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. The combined differential output current includes a plurality of differential output currents. First and second two-quadrant multipliers included in the MOS four-quadrant multiplier each have first and second pairs of transistors including sources connected in common to each other. A third pair of transistors is connected in cascode to the first pair of transistors as a load on the first pair of transistors. In each of the two-quadrant multipliers, the second pair of transistors has drains which are not connected in common to drains of the third pair of transistors. The second pair of transistors has gates respectively connected to drains of said first pair of transistors and sources of said third pair of transistors.

Abstract: In a bipolar OTA (operational transconductance amplifier) including a plurality of triple-tail cells, each of the plurality of triple-tail cells comprises a transistor pair of first and second transistors (Q1 and Q2) forming a differential input/output pair and a third transistor (Q3) applied with a control voltage (V.sub.C). The transistor pair and the third transistor are driven by a common tail current. The OTA has transistors (Q7 and Q8) for applying a dc offset voltage to an input signal of the differential input/output pair. The plurality of triple-tail cells have outputs connected in parallel.

Abstract: A current multiplier/divider circuit is provided, which is capable of any one of multiplication and division operations in a current mode without changing its configuration. This circuit includes a first set of m bipolar transistors and a second set of n bipolar transistors, where m.gtoreq.2) and n.gtoreq.2. A base of a (j-1)-th one of the transistors of the first set is connected to an emitter of the j-th transistor of the first set, where 2.ltoreq.j.ltoreq.m. A base of a (k-1)-th one of the transistors of the second set is connected to an emitter of the k-th transistor of the second set, where 2.ltoreq.k.ltoreq.n. A sum of V.sub.BE of the m transistors with respect to a specific electric potential, which is generated at a base of the m-th transistor in the first set, is equal to a sum of V.sub.BE of the n transistors, which is generated at a base of the n-th transistor in the second set.

Abstract: A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. Each of the first and second two-quadrant multipliers has first and second pairs of transistors having sources connected in common to each other, and a third pair of transistors connected in cascode to the first pair of transistors as a load on the first pair of transistors. In each of the two-quadrant multipliers, the second pair of transistors has drains not cross-coupled to drains of the third pair of transistors, the second pair of transistors has gates connected to drains of the first pair of transistors, respectively, and the third pair of transistors has gates connected in common to each other at a node. The differential output current of each two-quadrant multiplier contains at least a drain current of the second pair of transistors.

Abstract: A bipolar or MOS OTA is provided, in which no S/N degradation occurs due to compression and expansion of a signal, and low voltage operation can be realized at a power supply voltage of approximately 2 V for the input voltage range of approximately 1 V peak-to-peak or greater. This OTA includes a first differential pair of first and second transistors respectively driven by first and second current sources or sinks. A first resistor is connected to emitters or sources of the first and second transistors. A differential input signal is applied across these emitters or sources. This OTA further includes a second differential pair of third and fourth transistors. A second resistor is connected to emitters or sources of the third and fourth transistors. A current path is connected to the emitters or sources of the third and fourth transistors, thereby allowing a current to flow through the second resistor.

Abstract: A tripler for multiplying three input signals operable at a low power source voltage such as 3 V or less, which contains a first emitter-coupled pair of first and second bipolar transistors, a second emitter-coupled pair of third and fourth bipolar transistors, and a multiplier. Collectors of the first and third transistors are coupled together and those of the second and fourth transistors are coupled together. A tripler output is derived from the collectors coupled of the first and third transistors and those of the second and fourth transistors. Bases of the first and fourth transistors are coupled together and those of the second and third transistors are coupled together. A first input voltage is applied across the bases coupled of the first and is fourth transistors and those of the second and third transistors.

Abstract: In a bipolar multiplier for multiplying a first input signal and a second input signal, the bipolar multiplier comprises a quadritail cell including two transistor pairs driven by a common tail current. A conversion circuit is connected to an input side of the quadritail cell for carrying out inverse hyperbolic tangent conversion. The conversion circuit comprises first and second differential amplifiers which are supplied with the first and the second input signals, respectively.

Abstract: A multiplier containing first and second squaring circuits, in which the first squaring circuit has first and second differential transistor-pairs and the second squaring circuit has third and fourth ones. A positive output end of the first squaring circuit and an opposite output end of the second squaring circuit are coupled together, and an opposite output end of the first squaring circuit and a positive output end of the second squaring circuit are coupled together, which constitutes a pair of differential output ends of the multiplier. Sum and difference of first and second input voltages are applied to the differential input ends of the first and second squaring circuits, respectively. A first DC voltage is commonly applied across respective input ends of the first and second transistor-pairs, and a second one across the other input ends thereof. The second DC voltage is applied equal in polarity to the first DC voltage.

Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.

Abstract: At AGC amplifier circuit having a triple-tail cell including first, second and, third transistors whose emitter or sources are coupled together. The first and second transistors form a differential transistor-pair. The first, second and third transistors are driven by a single tail current. Bases or gates of the first and second transistors form input ends of the triple-tail cell to be applied with an input signal to be amplified. Collectors or drains of the first and second transistors form output ends of the triple-tail cell from which an amplified output signal with a variable gain is derived. A collector or drain of the third transistor form an output end of the triple-tail cell from which a rectified output signal is derived. A base or gate of the third transistor forms an input end of the first triple-tail cell to be applied with a gain control signal.

Abstract: An OTA capable of low-voltage operation at a voltage as low as approximately 1 V while restraining the circuit scale increase and keeping approximately the same input voltage range as that of the conventional one. This OTA has a differential pair of first and second bipolar or MOS transistors driven by a first constant current source, and a squarer driven by a second constant current source. The differential pair is applied with an input voltage and produces an output current of the OTA. The squarer is applied with the input voltage and produces differentially first and second output currents having a square-law characteristic. The first constant current source supplies a first constant current equal to a second constant current supplied by the second constant current source. The second output current of the squarer is supplied to the first constant current source.

Abstract: A multiplier core circuit having a novel circuit configuration, which is preferable for LSI. The circuit contains a quadritail circuit formed of first, second, third and fourth transistors whose emitters or sources are coupled together. Collectors or drains of the first and fourth transistors are coupled together and collectors or drains of the second and third transistors are coupled together. A sum of first and second input signals to be multiplied is applied to a base or gate of the first transistor with regard to a reference point. The first input signal is applied to a base or gate of the second transistor with regard to said reference point. The second input signal is applied to a base or gate of the third transistor with regard to the reference point. Neither the first input signal nor the second input signal are applied to a base or gate of the fourth transistor.

Abstract: A bipolar four-quadrant analog multiplier that is formed on a semiconductor integrated circuit device and is capable of low-voltage operation at a voltage as low as 1 V while the input voltage range providing a good linearity is enlarged. This multiplier contains a multitail cell made of a first transistor pair of first and second bipolar transistors, a second transistor pair of third and fourth bipolar transistors, and at least one bipolar transistor. The first and second transistors have output ends coupled together to form one of differential output ends of the multiplier. The third and fourth transistors have output ends coupled together to form the other of the differential output ends. The first to fifth transistors are driven by a common tail current. The first, second, third, fourth and fifth transistors are applied with (aV.sub.x +bV.sub.y), [(a-1)V.sub.x +(b-1)V.sub.y ], [(a-1)V.sub.x +bV.sub.y ], [aV.sub.x +(b-1)V.sub.y ], and [{a-(1/2}V.sub.x +{b-(1/2)}V.sub.y +V.sub.c ], respectively, where V.

Abstract: A tripler for multiplying three input signals operable at a low power source voltage such as 3 V or less, which contains a first emitter-coupled pair of first and second bipolar transistors, a second emitter-coupled pair of third and fourth bipolar transistors, and a multiplier. Collectors of the first and third transistors are coupled together and those of the second and fourth transistors are coupled together. A tripler output is derived from the collectors coupled to the first and third transistors and those of the second and fourth transistors. Bases of the first and fourth transistors are coupled together and those of the second and third transistors are coupled together. A first input voltage is applied across the bases coupled of the first and fourth transistors and those of the second and third transistors.

Abstract: A logarithmic amplifier circuit including a first triple-tail cell for rectifying an initial input signal to produce a first rectified output signal and a first amplified output signal, a second triple-tail cell for rectifying the first amplified output signal of the first triple-tail cell to produce a second rectified output signal and a second amplified output signal; and an adder for adding the first rectified output signal and the second rectified output signal. Each of the first and second triple-tail cells has first, second and third transistors whose emitters or sources are coupled together, said first and second transistors forming a differential pair. The differential pair and third transistor are driven by a single tail current. A base or gate of the third transistor are applied with ad c tuning voltage. Reduction of the circuit scale and total current consumption, low-voltage operation, and the logarithmic characteristics tuning can be realized.

Abstract: A reference current circuit comprises transistors Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4 and resistors R.sub.1 and R.sub.2. The resistor R.sub.1 is connected between base and collector electrodes of the transistor Q.sub.1. The resistor R.sub.2 is connected between base and collector electrodes of the transistor Q.sub.3. Emitter electrodes of the transistors Q.sub.1 and Q.sub.2 are connected to ground. The collector of the transistor Q.sub.1 is connected to a base electrode of the transistor Q.sub.2. The base electrode of the transistor Q.sub.1 is connected to the collector electrode of the transistor Q.sub.4. The collector electrode of the transistor Q.sub.2 is connected to the base electrode of the transistor Q.sub.3. Emitter electrodes of the transistors Q.sub.3 and Q.sub.4 are connected to a power supply terminal V.sub.CC which is supplied with a power supply voltage. Each of the transistors Q.sub.1 and Q.sub.3 has a first emitter area. Each of the transistors Q.sub.2 and Q.sub.

Abstract: An analog multiplier realizing drastically enlarged input voltage ranges with good linearity, low-voltage operation, and transconductance characteristics adjustment. This multiplier contains a first squarer applied differentially with first and second input signals in opposite phases, and a second squarer applied differentially with said first and second input signals in the same phase. Each of squarers is realized by a bipolar or MOS triple-tail cell including first, second and third transistors whose emitter or sources are coupled together and driven by a single tail current. Bases or gates of the first and second transistors form input ends of the squarer. Collectors or drains of the first and second transistors are coupled together to form one of output ends of the squarer. A collector or drain of the third transistor form the other thereof. A base or gate of the third transistor forms an input end to be applied with a bias signal. The transconductance varies dependent upon the applied bias voltage.

Abstract: A current reference circuit producing a reference current without temperature dependence and operating at a low supply voltage, which includes a first current source for producing a first constant current having a positive temperature coefficient, a second current source for producing a second constant current having a negative temperature coefficient, and an adder for adding the first and second constant currents to cancel their positive and negative temperature coefficients. The second current source contains first and second bipolar transistors and a resistor connected between a base and an emitter of the first bipolar transistor, and a bias subcircuit for supplying the reference current to the first bipolar transistor. The emitter of the first bipolar transistor is connected to an emitter of the second bipolar transistor, and a collector of the first bipolar transistor is connected to a base of the second bipolar transistor.