Abstract: An OTA having a completely linear transconductance characteristic or a squarer having an accurate square-law characteristic is provided, which is comprised of first and second differential circuits. The first differential circuit has a first differential pair of first and second MOSFETs whose sources are coupled together and a third MOSFET serving as a bypass transistor for the first differential pair. The first differential pair is driven by a first constant tail current. The second MOSFET is driven by a first constant driving current. The second differential circuit has a second differential pair of fourth and fifth MOSFETs whose sources are coupled together and a sixth MOSFET serving as a bypass transistor for the second differential pair. The second differential pair is driven by a second constant tail current. The fifth MOSFET is driven by a second constant driving current.

Abstract: A three-input multiplier core circuit for multiplying first, second, and third initial input voltages V.sub.x, V.sub.y, and V.sub.z is provided, which is operable at a low supply voltage such as approximately 1 V is provided. This circuit includes an octtail cell having first to eighth bipolar transistors whose emitters are coupled together to be connected to a common constant current source/sink. Collectors of the first to fourth transistors are coupled together to form one of a pair of output terminals, and collectors of the fifth to eighth transistors are coupled together to form the other of the pair thereof. An output including the multiplication result is differentially derived from the pair of output terminals. Bases of the first to eighth transistors are respectively applied with voltages V.sub.1 to V.sub.8, where V.sub.1 =aV.sub.x +bV.sub.y +cV.sub.z, V.sub.2 =aV.sub.x +(b-1)V.sub.y +(c-1)V.sub.z, V.sub.3 =(a-1)V.sub.x +bV.sub.y +(c-1)V.sub.z, V.sub.4 =(a-1)V.sub.x +(b-1)V.sub.y +cV.sub.z, V.sub.

Abstract: A tunable CMOS OTA is provided, which improves the transconductance linearity with a simple circuit configuration. This OTA is comprised of (a) a differential input pair of first and second MOSFETs, (b) a first resistor connected to sources of the first and second MOSFETs, (c) a current source/sink for supplying/sinking a variable driving current to the differential input pair, and (d) an output circuit for the differential input pair. A differential input voltage is applied across gates of the first and second MOSFETs to generate a first pair of differential output currents. The current flowing through the first resistor is proportional to the applied differential input voltage. The first pair of differential output currents are applied to drains of third and fourth MOSFETs of the output circuit, respectively, thereby generating a first bias voltage at the drain of the third MOSFET and a second bias voltage at the drain of the fourth MOSFET.

Abstract: A current reference circuit is capable of operation at a very low supply voltage, such as 1 volt. The current reference circuit is composed of a current mirror circuit, serving as an inverse PTAT (i.e., inversely proportional to absolute temperature) subcircuit, and a PTAT subcircuit for driving the current mirror circuit. The current mirror circuit and the PTAT subcircuit are mutually biased to each other. First and second constant currents produced by the PTAT subcircuit are supplied to the current mirror circuit as its reference and mirror currents, thereby cancelling the temperature coefficients of the first and second constant currents.

Abstract: A two-quadrant multiplier for multiplying first and second signals, which can realize wide input voltage ranges at a low supply voltage such as 3 or 3.3 V, has a multitail cell. This multitail cell contains a pair of first and second transistors having differential input ends and differential output ends, a third transistor having an input end, and a constant current source for driving the pair and the third transistor. The first signal is applied across the differential input ends of the pair, and the second signal is applied in a single polarity (e.g., either a positive or negative polarity) to the input end of the third transistor. An output signal of the multiplier is a multiplication result of the first and second signals which is differentially derived from the differential output ends of the pair. At least one additional transistor may be provided, an input end of which is coupled with the input ends of the third transistor to be applied with the second signal.

Abstract: By using the two square-law circuits for squaring the common mode and orthogonal components of the carrier wave and by using the multiplying circuit for multiplying these squared signals, the Costas loop carrier recovery circuit can be constituted. The carrier recovery circuit is constituted such that a phase synchronous circuit constituted by a PLL is controlled by a signal obtained by removing a sign component from an input carrier wave.

Abstract: A bipolar OTA having an improved S/N level is provided, which includes first, second, and third balanced differential pairs. The first balanced differential pair is formed by first and second bipolar transistors whose emitters are connected to one another through a common emitter resistor. The first and second transistors are driven by corresponding constant current sources/sinks, respectively. The second balanced differential pair is formed by third and fourth transistors whose emitters are coupled together to be connected to a collector of the first transistor. The third balanced differential pair is formed by fifth and sixth transistors whose emitters are coupled together to be connected to a collector of the second transistor. The third and fourth balanced differential pairs are driven by the collector currents of the first and second transistors, respectively. A control voltage is applied across bases of the third and fourth transistors and bases of the fifth and sixth transistors.

Abstract: A bipolar OTA having a wide input voltage range is provided without increasing the circuit scale and current consumption. This OTA includes first to n-th differential pairs of first to 2n-th bipolar transistors whose emitters are coupled together, where n.gtoreq.2; and a common current source/sink connected to the emitters of the first to 2n-th transistors. The first to 2n-th transistors are driven by a common tail current produced by the common current source/sink. The transistors of each of the second to n-th differential pairs have a same emitter area K.sub.1 to K.sub.n-1 times as large as that of the first and second transistors, where K.sub.1 to K.sub.n-1 >1. A first input voltage as an input signal to be amplified is differentially applied across bases of the first and second transistors of the first differential pair. A second to n-th input voltages are differentially applied across corresponding bases of the third to 2n-th transistors, respectively.

Abstract: A bipolar OTA having a wide input voltage range is provided without increasing the circuit scale and current consumption. This OTA includes a first differential pair of emitter-coupled first and second bipolar transistors, a second differential pair of emitter-coupled third and fourth bipolar transistors, a common current source or sink connected to the coupled emitters of the first to fourth transistors. The first to fourth transistors are driven by a common tail current produced by the common current source or sink. A first input voltage as an input signal to be amplified is differentially applied across the bases of the first and second transistors. A second input voltage, which is produced by attenuating the first input voltage, is differentially applied across the bases of the third and fourth transistors. First and second dc offset voltages are applied to the bases of the third and fourth transistors, respectively.

Abstract: A bipolar four-quadrant analog multiplier that is formed on a semiconductor integrated circuit device and is capable of low-voltage operation at a voltage as low as 1 V while the input voltage range providing a good linearity is enlarged. This multiplier contains a multitail cell made of a first transistor pair of first and second bipolar transistors, a second transistor pair of third and fourth bipolar transistors, and at least one bipolar transistor. The first and second transistors have output ends coupled together to form one of differential output ends of the multiplier. The third and fourth transistors have output ends coupled together to form the other of the differential output ends. The first to fifth transistors are driven by a common tail current. The first, second, third, fourth and fifth transistors are applied with (aV.sub.x +bV.sub.y), ((a-1)V.sub.x +(b-1)V.sub.y), ((a-1)V.sub.x +bV.sub.y), (aV.sub.x +(b-1)V.sub.y), and ({a-(1/2}V.sub.x +{b-(1/2)}V.sub.y +V.sub.c), respectively, where V.sub.

Abstract: An analog multiplier that decreases the circuit current consumption is provided. This multiplier includes a first triple-tail cell of first, second, and third transistors driven by a first tail current, and a second triple-tail cell of fourth, fifth, and sixth transistors driven by a second tail current. First and second constant current sources supplies first and second constant currents to the third and sixth transistors, respectively. The first and second tail currents are controlled by first and second tail current controllers, respectively The first and second tail current controllers controls the first and second tail currents so that the current changes of the third and sixth transistors are canceled, respectively, where the current changes are caused by the second input voltage applied across the input terminals of the third and sixth transistors.

Abstract: A bipolar analog multiplier is provided, which is capable of complete four-quadrant multiplication operation. This multiplier has a quadritail cell serving as a multiplier core circuit, and an input circuit. In the input circuit, first and second linear V-I converters linearly convert the applied first and second initial input voltages to first and third pairs of differential output currents, respectively. The first and third pairs of differential output currents are converted to first and second differential output voltages through logarithmic compression, respectively. First and second linear transconductance amplifiers amplify the first and second differential output voltage to generate second and fourth pairs of differential output currents. The second and fourth pairs of differential output currents are added to generate first, second, third, and fourth input currents.

Abstract: A voltage reference circuit capable of realization of two reference voltages having different temperature coefficients is provided. This circuit includes a first bipolar transistor, a second bipolar transistor, and first, second, and third resistors. An emitter of the first transistor is directly connected to a fixed voltage level. An emitter of the second transistor is connected to the fixed voltage level through the first resistor. A collector of the first transistor is connected to a base of the second transistor. A collector of the second transistor is connected to a base of the first transistor. A first end of the second resistor is connected to the connection point of the collector of the first transistor and the base of the second transistor. A first end of the third resistor is connected to the connection point of the collector of the second transistor and the base of the first transistor. The first transistor is driven by a first driving current through the second resistor.

Abstract: A bipolar or MOS current reference circuit is provided, which generates a reference current having no temperature dependence and which is able to be operated by a single battery having a supply voltage of approximately 1 V. This circuit includes a first transistor having an emitter or source and a base or gate connected through a resistor, a first current mirror subcircuit generating a first mirror current of an input current flowing through the resistor, and a second current mirror subcircuit generating a second current of the input current flowing through the resistor. The first mirror current has a negative temperature coefficient. The second mirror current has a positive temperature coefficient. The first and second mirror currents are added to generate a sum current having no temperature dependence, which is derived as a reference current. The sum current is supplied to the first transistor to thereby drive the first transistor.

Abstract: A four-quadrant multiplier which is constructed from two squaring circuits using the quarter-square technique and is suitable for an integrated circuit (IC) or a large-scale integrated circuit (LSI). Each of the squaring circuits has a pair of differential input terminals, an output terminal and two differential pairs. Each of differential pairs is composed of first and second transistors whose sources or emitters are connected in common, receives a differential input voltage impressed between the differential input terminals. In each differential pair, a constant current source of a predetermined current value and an dynamic bias current source are inserted in parallel between the common sources or the common emitters and the grounding point. The dynamic bias current source is realized by a current mirror circuit which outputs current equal to the drain current or the collector current of the second transistor.

Abstract: A voltage adder/subtractor circuit is provided, which has an improved frequency characteristic and which is operable at a low supply voltage such as approximately 1.1 V. This circuit includes a first differential pair of emitter/source-coupled first and second transistors driven by a first constant current, and a second differential pair of emitter/source-coupled third and fourth transistors driven by a second constant current having a same current value as that of the first constant current. A third constant current source/sink serving as a common load for the second and third transistors is connected to the collector/drain of the second transistor and the coupled collector/drain and base/gate of the third transistor. The third constant current source/sink supplies/sinks a third constant current having a same current value as that of the first constant current. A first input voltage is differentially applied across bases/gates of the first and second transistors.

Abstract: A multiplier containing first and second quadritail cells. The first quadritail cell has a first pair of first and second transistors, a second pair of third and fourth transistors, and a first constant current source for driving the first and second pairs. The second quadritail cell has a third pair of fifth and sixth transistors, a fourth pair of seventh and eighth transistors, and a second constant current source for driving the third and fourth pairs. A first input voltage is applied between input ends of the first and fourth transistors and is applied between input ends of the fifth and eighth transistors. A second input voltage is applied between input ends coupled together of the second and third transistors and the input ends coupled together of the sixth and seventh transistors.

Abstract: A multiplier includes first through fourth transistors (Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4) and a current source (I.sub.0) The first transistor has a base electrode connected to a first input terminal (T1) and a collector electrode connected to a first output terminal (T5). The second transistor has a base electrode connected to a second input terminal (T2) and a collector electrode connected to a second output terminal (T6). The third transistor has a base electrode connected to a third input terminal (T3) and a collector electrode connected to the second output terminal. The fourth transistor has a base electrode connected to a fourth input terminal (T4) and a collector electrode connected to the first output terminal. Supplied with voltages of V.sub.1 and V.sub.2, a voltage supplying circuit produces and supplies voltages of (1/2)V.sub.1, (-1/2)V.sub.1, {(1/2)V.sub.1 -V.sub.2 }, and {(-1/2)V.sub.1 -V.sub.2 } to the input terminals. The output terminals are supplied with first and second output currents.

Abstract: A differential circuit is provided, which makes it possible to realize an ideal linear behavior with respect to an input signal. This circuit includes a voltage-current converter, a current-voltage converter, and a triple-tail cell. The voltage-current converter converts an initial input voltage to generate first and second differential output currents. The current-voltage converter converts the first and second output currents to generate first and second output voltages. The triple-tail cell has first, second, and third transistors driven by a common constant current. The first and second transistors form a differential pair. The first and second output voltages are differentially applied across input ends of the differential pair. The third transistor serves as a bypass transistor for the common constant current. An input end of the third transistor is applied with a bias voltage. An output current of the differential circuit is derived from output ends of the differential pair.

Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.