Abstract: An MOS OTA that enables to provide superior transconductance linearity within a wider input voltage range without increase in circuit scale and to be formed on a semiconductor integrated circuit device. The MOS OTA includes a differential pair of first and second MOSFETs whose sources are coupled together, and a quadritail circuit for driving the differential pair by its output signal having a square-law characteristic. The quadritail circuit contains a first transistor pair of third and fourth MOSFETs, a second transistor pair of fifth and sixth MOSFETs, and a constant current source or sink for driving the first and second transistor pairs. Gates of the third and fourth MOSFETs are applied with the differential input signal. Gates of the fifth and sixth MOSFETs are coupled together to be applied with a dc voltage of the differential input signal. The transconductance nonlinearity of the differential pair is compensated by the output current of the quadritail circuit.

Abstract: Disclosed is a semiconductor integrated circuit which have a pair of transistors Q11, Q12 with a first polarity being differentially inputted with first logical values A(+) and A(-), a first constant current source I11 for driving the pair of transistors with the first polarity, two pairs of transistors Q13, Q14 and Q15, Q16 with a second polarity, each of the two pairs of transistors being differentially inputted with second logical values B(+) and B(-) and being connected to a drain of each of the pair of transistors with the first polarity, a second and third constant current sources I12, I13 for driving the two pairs of transistors, respectively, and load resistors R11, R12 which are connected to the two pairs of transistors, respectively.

Abstract: In a squaring circuit which responds to an input voltage to produce an output current and which is specified by a squaring characteristic between the input voltage and the output current, first, second, and third transistors are connected in common to a constant current source while the first and the second transistors are connected to input terminals for the input voltage and also connected in common to a single output terminal. The third transistor is connected to another output terminal and supplied with a d.c. voltage as a control signal. The output current appears between the output terminals as a differential output current. The squaring characteristic is kept even when the input voltage is widely varied. Each of the first through the third transistors may be either a bipolar transistor or a MOS transistor.

Abstract: A multiplier in which simplification of a circuit configuration and reduction of a current consumption can be realized. There are provided with first, second, third and fourth pairs of transistors whose capacities are the same with each other and these four pairs are driven by a constant current source, respectively. A sum of first and second input voltage is applied in positive phase to an input end of the first pair and the sum is applied in opposite phase to the other input end thereof. A difference of the first and second input voltages is applied in positive phase to an input end of the second pair and the difference is applied in opposite phase to the other input end thereof. Input ends of the third pair and those of the fourth pair are coupled together to be applied with a direct current voltage.

Abstract: A tunable MOS operational transconductance amplifier which outputs a differential output current in response to a differential input voltage. The amplifier has a tail current source, a first transistor pair, a second transistor pair and a third transistor pair. The sources of the first and second transistor pairs are connected in common to the tail current source. The third transistor pair is connected in cascode to the first transistor pair. The gates of the second transistor pair are connected to drains of the first transistor pair, respectively. The gates of one of the first transistor pair are connected to each other and a tuning voltage is applied to the gates of the one pair. The differential input voltage is applied between the gates of the other of the first transistor pair and the third transistor pair. The differential output current of the amplifier includes at least the differential drain current of the second transistor pair.

Abstract: A multiplier includes first through fourth transistors (Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4) and a current source (I.sub.0). The first transistor has a base electrode connected to a first input terminal (T1) and a collector electrode connected to a first output terminal (T5). The second transistor has a base electrode connected to a second input terminal (T2) and a collector electrode connected to a second output terminal (T6). The third transistor has a base electrode connected to a third input terminal (T3) and a collector electrode connected to the second output terminal. The fourth transistor has a base electrode connected to a fourth input terminal (T4) and a collector electrode connected to the first output terminal. Supplied with voltages of V.sub.1 and V.sub.2, a voltage supplying circuit produces and supplies voltages of (1/2)V.sub.1, (-1/2)V.sub.1, {(1/2)V.sub.1 -V.sub.2 }, and {(-1/2)V.sub.1 -V.sub.2 } to the input terminals. The output terminals are supplied with first and second output currents.

Abstract: A logarithmic amplification circuit is provided which is composed of a differential amplifier, a plurality of full-wave rectifiers including two half-wave rectifiers connected so as to have their input signals inverse in phase to each other and respectively receiving an output signal of the differential amplifier, and an adder for adding the output signals of the full-wave rectifier. Each of the half-wave rectifiers includes a differential transistor pair only one of which has an emitter resistor.

Abstract: In an electronic circuit operable as a local oscillator frequency multiplier and mixing circuit, a squaring circuit is operated in response to a local oscillator frequency signal of a local oscillator frequency and is connected to a constant current circuit or a transistor circuit responsive to an input high frequency signal of a high frequency so as to obtain a frequency equal to a sum of an integral multiple or double of the local oscillator frequency and the high frequency and a difference between the integral multiple of the local oscillator frequency and the high frequency. The squaring circuit may be formed by four transistors connected in pairs while the transistor circuit may be structured by a cross-connected, emitter-coupled transistor circuit, an unbalanced emitter-coupled transistor circuit, or a pair of transistors. A control signal, such as an AGC control signal, may be given to the transistor circuit or the constant current circuit.

Abstract: An operational transconductance amplifier having a good transconductance linearlity within a wide input voltage range that can be realized easily without increase in chip area. There are a first balanced differential pair of first and second MOS transistors that are driven by a first constant current source, and a second balanced differential pair of third and fourth MOS transistors that are driven by a second constant current source. The first, second, third and fourth transistors have the same transconductance parameter. Drains of the first and fourth transistors are coupled together and drains of the second and third transistors are coupled together. A differential output current of the amplifier is derived from the output ends of the first and fourth transistors and the output ends of the second and third transistors. Gates of the first and third transistors are applied with an input voltage. Gates of the third and fourth transistors are applied with a voltage produced by dividing the input voltage.

Abstract: A logarithmic amplifier circuit is provided, which contains a differential amplifier, a first rectifier for rectifying an initial input signal and for generating a first rectified output signal, a second rectifier for rectifying an amplified output signal from the differential amplifier and for generating a second rectified output signal, and an adder for adding the first and second rectified output signals to produce an output signal having a logarithmic characteristic. The first and second rectifiers each is made of a triple-tail cell. The cell contains first, second and third emitter- or source-coupled transistors and a constant current source for driving the transistors. An input signal is applied across bases or gates of the first and second transistors, and a dc voltage is applied to a base or gate of the third transistor. An output current is outputted through the coupled collectors or drains of the first and second transistors or through the collector or drain of the third transistor.

Abstract: A constant-current circuit which has four MOS transistors. The first and second MOS transistors are driven at a constant current ratio corresponding to a ratio of gate-width and gate-length ratios of the third and fourth MOS transistors. The third and fourth MOS transistors are configured as a current mirror circuit, and are chosen to have different gate-width and gate-length ratios from one another.

Abstract: A logarithmic amplifying circuit with a reduced power dissipation and suitable for applying to an integrated circuit. The logarithmic amplifying circuit has cascade-connected differential amplifiers, a rectifier connected to each if the amplifiers and an adder for adding the output currents of the rectifiers. Each of the rectifiers has a differential pair composed of a plurality of transistors emitter-coupled or source-coupled, a constant current source for a tail current of the differential pair and an offset voltage source for superimposing a DC offset voltage on a differential input voltage to be supplied to the differential pair.

Abstract: A differential amplifier circuit having an improved transconductance linearity, which includes a first to fourth unbalanced differential pairs of MOS transistors. In each differential pair, a ratio (W/L) of a gate-width W and a gate-length L of one transistor is different from that of the other transistor. Gates of the transistors having smaller ratios of the first and third pairs and gates of the transistors having larger ratios of the second and fourth pairs are coupled together to form one of differential input ends. Gates of the transistors having larger ratios of the first and third pairs and gates of the transistors having smaller ratios of the second and fourth pairs are coupled together to form the other of the input ends. Drains of the transistors having smaller ratios of the first and second pairs and drains of the transistors having larger ratios of the third and fourth pairs are coupled together to form one of differential output ends.

Abstract: In a MOS operational transconductance amplifier including a MOS transistor differential pair, first to fourth current mirrors are provided between a voltage supply and a reference potential. The second and fourth current mirrors are connected together to a common node to which the channels of MOS transistor differential pair are connected. A first MOS transistor is connected between the voltage supply and a first constant current sink, and a second MOS transistor is connected at one end to the first current mirror and at the other end to the first constant current sink and the second current mirror. A third MOS transistor is connected at one end to the third current mirror and at the other end to the second constant current sink and the fourth current mirror, and a fourth MOS transistor is connected between the voltage supply and the second constant current sink.

Abstract: A differential amplifier circuit having a superior transconductance linearity within a wider input voltage range, which includes a first differential pair of transistors and a driver circuit for driving the differential pair by its output current. This output current has a square-law characteristic to compensate in nonlinearity the transconductance of the differential pair. The driver circuit is a squarer or a quadritail circuit. A signal to be amplified is applied to a pair of input terminals. Input ends of the differential pair are connected to a pair of input terminals to be applied with a first input signal. Input ends of the driver circuit is connected to the pair of input terminals to be applied with a second input signal. The first and second input signals are proportional in amplitude to the signal to be amplified.

Abstract: In a logarithmic intermediate frequency amplifier circuit including first through M-th intermediate frequency amplifiers which are connected in cascade and first through M-th double balanced differential circuits which are connected to the first through the M-th intermediate frequency amplifiers, respectively, each of the first through the M-th double balanced differential circuits comprises primary, secondary, and tertiary differential circuits. The primary differential circuit includes a pair of transistors each of which is one of NPN and PNP types and which are connected to a first constant current source. The secondary differential circuit includes a pair of transistors each of which is another one of NPN and PNP types and which are connected to a second constant current source. The tertiary differential circuit includes a pair of transistors each of which is the other one of the NPN and the PNP types and which are connected to a third constant current source.

Abstract: A logarithmic amplifying circuit with a wide input dynamic range using cascade-connected differential amplifiers, a rectifier connected to each of the amplifiers and an adder for adding the output currents of the rectifiers. The rectifiers each have a quadritail cell which consists of a single tall current source and four transistors. The transistors are emitter-connected or source-connected and driven by the tail current source. The bases or gates of the first and second transistors of the quadritail cell are connected to respective terminals of a differential input pair of the rectifier. The collectors or drains of the first and second transistors are connected in common to one terminal of a differential output pair of the rectifier, and the collectors or drains of the third and fourth transistors are connected in common to the other output terminal of the rectifier.

Abstract: A C-MOS logarithmic IF amplifier is provided which comprises a plurality of IF amplifiers cascade-connected to each other through a first coupling capacitor, a plurality of rectifiers each receiving a signal from the corresponding one of the plurality of IF amplifiers through a second coupling capacitor different in capacity from the first coupling capacitor, and an adder for adding the output signals of these rectifiers to each other. The first and second coupling capacitors are preferable to be connected in series to cascade-connect those IF amplifiers therethrough. Each of the rectifiers is applied with an output signal of the corresponding one of the IF amplifier from the connection point of the corresponding first and second coupling capacitors.

Abstract: A multiplier having first and second quadritail circuits, each of which has two pairs of transistors whose capacities are the same, respectively, and is driven by a constant current source. In the first quadritail circuit, input ends of a first pair are respectively applied with voltages .+-.(V.sub.1 +V.sub.2), and input ends of a second pair are connected in common to be biased by a middle point voltage of the voltage applied between the input ends of the first pair. In the second quadritail circuit, input ends of a third pair are respectively applied with voltages .+-.(V.sub.1 -V.sub.2), and input ends of a fourth pair are connected in common to be biased by a middle point voltage of the voltage applied between the input ends of the third pair.

Abstract: A reference voltage generating circuit comprising a first and second transistors whose base-to-emitter voltages are different from each other and a constant current source to drive said respective transistors. Since the base-to-emitter voltages are different from each other, the circuit scarcely has a temperature characteristic with a reduced circuit scale. The first and second transistors preferably have different emitter areas. The current source is preferably a current mirror circuit composed of third and fourth transistors whose emitter areas are different from each other to drive the first and second transistors by different currents.