Patents by Inventor Kazuhiro Matsuo

Kazuhiro Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403642
    Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Matsuo, Akiko Sekihara, Akira Takashima, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
  • Patent number: 10396280
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shinji Mori, Masayuki Tanaka, Kazuhiro Matsuo, Kenichiro Toratani, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Yuta Saito
  • Patent number: 10304850
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a stacked body provided on the substrate, a plurality of electrode films being stacked to be separated from each other in the stacked body, a semiconductor pillar piercing the plurality of electrode films, a first insulating film provided between the semiconductor pillar and the electrode films, a second insulating film provided between the semiconductor pillar and the first insulating film; and a third insulating film provided between the first insulating film and the electrode films. The first insulating film includes silicon, nitrogen, oxygen, and carbon.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Publication number: 20190139981
    Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.
    Type: Application
    Filed: August 7, 2018
    Publication date: May 9, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Matsuo, Akiko Sekihara, Akira Takashima, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
  • Publication number: 20190027538
    Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.
    Type: Application
    Filed: February 8, 2018
    Publication date: January 24, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Takaumi Morita, Masayuki Tanaka, Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Kenichiro Toratani, Hisashi Okuchi
  • Publication number: 20180277757
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including(a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji MORI, Masayuki TANAKA, Kazuhiro MATSUO, Kenichiro TORATANI, Keiichi SAWA, Kazuhisa MATSUDA, Atsushi TAKAHASHI, Yuta SAITO
  • Patent number: 9785039
    Abstract: A wavelength conversion member includes a substrate, a dichroic mirror layer, an SiO2 layer, a ZnO layer, and a phosphor layer, which are sequentially stacked from the substrate. The dichroic mirror layer reflects at least part of light incident from the above. The phosphor layer includes a plurality of phosphors and ZnO between the phosphors.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 10, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGMENT CO., LTD.
    Inventors: Atsushi Motoya, Kenta Watanabe, Ran Zheng, Sachiko Azuma, Yoshihisa Nagasaki, Takahiro Hamada, Mitsuru Nitta, Takashi Maniwa, Toshio Mori, Kazuhiro Matsuo
  • Patent number: 9695512
    Abstract: In one embodiment, a semiconductor manufacturing system includes a film forming apparatus configured to form a film on a surface of a wafer. The system further includes a gas supply module configured to supply at least a type of source gas for the film into the film forming apparatus. The system further includes a measurement module configured to measure a discharge amount of an exhaust gas from the film forming apparatus. The system further includes a controller configured to calculate a value corresponding to a surface area of the wafer based on the discharge amount of the exhaust gas from the film forming apparatus, and to control a supply amount of the source gas to the film forming apparatus based on the value corresponding to the surface area of the wafer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: July 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Matsuo, Fumiki Aiso
  • Publication number: 20170067153
    Abstract: In one embodiment, a semiconductor manufacturing system includes a processing apparatus configured to process a wafer, an exhaust pump configured to discharge an exhaust gas from the processing apparatus, and a measurement module configured to measure a value that indicates operation of the exhaust pump. The system further includes a controller configured to feed a first gas for pushing out a fragment of a product that is generated by the exhaust gas and is attached to or flows into the exhaust pump, a second gas for cooling the exhaust pump, a third gas for changing characteristics of the product attached to the exhaust pump, or a fourth gas to react with the product attached to the exhaust pump, into the exhaust pump based on the value measured by the measurement module.
    Type: Application
    Filed: February 5, 2016
    Publication date: March 9, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazuhiro MATSUO
  • Publication number: 20170069654
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a stacked body provided on the substrate, a plurality of electrode films being stacked to be separated from each other in the stacked body, a semiconductor pillar piercing the plurality of electrode films, a first insulating film provided between the semiconductor pillar and the electrode films, a second insulating film provided between the semiconductor pillar and the first insulating film; and a third insulating film provided between the first insulating film and the electrode films. The first insulating film includes silicon, nitrogen, oxygen, and carbon.
    Type: Application
    Filed: February 1, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro MATSUO, Masayuki TANAKA, Shinji Mori, Kenichiro Toratani
  • Publication number: 20170062460
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including: a first electrode layer including a first portion and a second portion thicker than the first portion in stacking direction of the stacked body; and an insulating layer provided between the first electrode layer and the substrate; a semiconductor film provided in the stacked body and extending in the stacking direction; a charge storage film provided between the semiconductor film and the first electrode layer; and a first intermediate insulating film provided between the charge storage film and the first electrode layer. The distance between the semiconductor film and the second portion is shorter than the distance between the semiconductor film and the first portion. The first intermediate insulating film extends in the stacking direction.
    Type: Application
    Filed: January 28, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke NISHIDA, Kazuhiro Matsuo
  • Patent number: 9450108
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion provided on the semiconductor portion, a silicon-containing portion provided on the first oxygen-containing portion, a first film provided on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion provided on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion provided on the first high dielectric insulating portion, a second high dielectric insulating portion provided on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion provided on the second high dielectric insulating portion, and a second film provided on the third oxygen-containing portion.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
  • Publication number: 20160258058
    Abstract: A semiconductor manufacturing apparatus in this embodiment includes a reactor, a pump, an exhaust pipe and a mesh member. The reactor houses a semiconductor substrate to treat the semiconductor substrate. The pump exhausts a gas inside the reactor. The exhaust pipe connects between the reactor and the pump. The mesh member is located at a flow inlet of the pump for the gas or in the exhaust pipe and has a main plane having a plurality of meshes arranged thereon. The mesh member has a protrusion and/or protruding shape projecting upstream of the gas.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Nakahara, Kazuhiro Matsuo
  • Publication number: 20160208382
    Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a reaction chamber that is capable of housing a semiconductor substrate and is capable of forming a deposited film on a surface of the semiconductor substrate. A first container stores a source of the deposited film. A second container stores a source gas generated in the first container, and supplies the source gas to the reaction chamber. A first pipe connects the first container and the second container. A second pipe supplies an inert gas to the second container.
    Type: Application
    Filed: July 29, 2015
    Publication date: July 21, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensei Takahashi, Kazuhiro Matsuo, Fumiki Aiso
  • Patent number: 9355846
    Abstract: According to one embodiment, a method for forming a semiconductor device includes: forming a first underlayer film that contains a first chemical element selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals; forming, on the first underlayer film, a second underlayer film that contains a second chemical element selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals, the second chemical element being an chemical element not contained in the first underlayer film; and forming, on the second underlayer film, a silicon oxide film by a CVD or ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group, and an amino group, or a silicon source of a siloxane system.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 31, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Kenichiro Toratani, Kazuhiro Matsuo
  • Publication number: 20160077415
    Abstract: A wavelength conversion member includes a substrate, a dichroic mirror layer, an SiO2 layer, a ZnO layer, and a phosphor layer, which are sequentially stacked from the substrate. The dichroic mirror layer reflects at least part of light incident from the above. The phosphor layer includes a plurality of phosphors and ZnO between the phosphors.
    Type: Application
    Filed: August 21, 2015
    Publication date: March 17, 2016
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi MOTOYA, Kenta WATANABE, Ran ZHENG, Sachiko AZUMA, Yoshihisa NAGASAKI, Takahiro HAMADA, Mitsuru NITTA, Takashi MANIWA, Toshio MORI, Kazuhiro MATSUO
  • Publication number: 20160064408
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer; a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a side surface of the charge accumulation layer. The inter-layer insulating layer comprises: a first silicon oxide layer; a first metal oxide layer; and a first silicon nitride layer. The first metal oxide layer is formed on a first surface facing the conductive layer, of the first silicon oxide layer. The first silicon nitride layer is formed on the first surface via the first metal oxide layer.
    Type: Application
    Filed: July 22, 2015
    Publication date: March 3, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao SHINGU, Masaaki HIGUCHI, Katsuyuki SEKINE, Kazuhiro MATSUO
  • Publication number: 20160060762
    Abstract: In one embodiment, a semiconductor manufacturing system includes a film forming apparatus configured to form a film on a surface of a wafer. The system further includes a gas supply module configured to supply at least a type of source gas for the film into the film forming apparatus. The system further includes a measurement module configured to measure a discharge amount of an exhaust gas from the film forming apparatus. The system further includes a controller configured to calculate a value corresponding to a surface area of the wafer based on the discharge amount of the exhaust gas from the film forming apparatus, and to control a supply amount of the source gas to the film forming apparatus based on the value corresponding to the surface area of the wafer.
    Type: Application
    Filed: February 5, 2015
    Publication date: March 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro MATSUO, Fumiki Aiso
  • Patent number: 9224874
    Abstract: A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A tunnel insulating film is provided on the semiconductor substrate. A charge accumulation layer is provided on the tunnel insulating film. An intermediate dielectric film is provided on the charge accumulation layer. A control gate electrode is formed on the intermediate dielectric film. The intermediate dielectric film includes a laminated film of silicon oxide films of multiple layers and silicon nitride films of at least one layer, and a silicon oxynitride film provided between adjacent ones of the silicon oxide films and the silicon nitride films.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Masao Shingu, Kensei Takahashi, Fumiki Aiso
  • Patent number: RE47591
    Abstract: An LED lamp provides a strong red color with a natural appearance. The LED lamp is provided with an LED module and a filter. The LED module includes a blue LED with a main emission peak in the 440 nm to 460 nm wavelength band, a green/yellow phosphor that is excited by light emitted by the blue LED, and a red phosphor that is excited by light emitted by at least one of the blue LED and the green/yellow phosphor. The filter reduces the spectral radiation intensity of at least a portion of the 570 nm to 590 nm wavelength band among light emitted by the LED module.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 3, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoko Matsubayashi, Hiroshi Yagi, Masanori Shimizu, Yoshio Manabe, Atsushi Motoya, Kazuhiro Matsuo, Toshio Mori