Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit, whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.

Abstract: To execute cache data identity control between disk controllers in plural disk controllers provided with each cache. To prevent a trouble from being propagated to another disk controller even if the trouble occurs in a specific disk controller. The identity control of data is executed via a communication means between disk controllers. In case update access from a host is received, data in a cache memory of a disk controller that controls at least a data storage drive is updated. It is desirable that a cache area is divided into an area for a drive controlled by the disk controller and an area for a drive controlled by another disk controller and is used.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A changeover switch switches connection between an antenna and a transmitter amplifier and connection between the antenna and a receiver low noise amplifier, from one to the other. A first wire having characteristic impedance of 50 .OMEGA. connects the antenna and the changeover switch. A receiver matching circuit matches input impedance of the receiver low noise amplifier with the output impedance of the transmitter amplifier. An antenna side matching circuit matches the input impedance of the receiver low noise amplifier, which is matched with the output impedance of the transmitter amplifier by the receiver matching circuit, and the output impedance of the transmitter amplifier with the characteristic impedance of the first wire. The transmitter amplifier is connected with the changeover switch via a first coupling capacitance, and the receiver matching circuit is connected with the changeover switch via a second coupling capacitance.

Abstract: On a GaAs substrate are provided a buffer layer comprising an Undope-GaAs layer, a first n-InGaAs layer having an In composition ratio of 0.2, a second n-InGaAs layer having an In composition ratio of 0.02, a contact layer comprising an N.sup.+ type GaAs layer, a gate electrode, a source electrode, and a drain electrode. The first n-InGaAs layer and the second n-InGaAs layer form active layers in which an operating current flows. The second n-InGaAs layer having excellent crystallinity is formed on the first n-InGaAs layer. Consequently, a field effect transistor which displays a super low distortion characteristic having IP2 of 67.2 dBm and IP3 of 35 dBm can be manufactured with good reproducibility.

Abstract: A field effect transistor structure is disclosed. A SiN insulating layer is deposited on a semi-insulating GaAs substrate. A slit window is formed to determine the effective gate length formed after pattern forming a high density n-type region by ion implanting on the semi-insulating GaAs substrate. A n-type active region is formed by ion implanting a p-type impurity. An insulating layer is used as an ion implanting mask in a partial compensation of the n-type region. At the same time, a p-type region is formed under the n-type active region. A high melting point to make a Schottky gate electrode is deposited and then annealed. The high melting point metal layer is left as a gate electrode and a low specific resistance connecting metal layer is deposited on the gate electrode.

Abstract: An information recording and reproducing apparatus which has a memory portion which uses the Bloch lines occurring at the magnetic domain walls at the periphery of magnetic domains present in magnetic garnet films as the information carrier, a drive portion to write information into or read information from the said memory portion, and in which the memory portion is constructed to be connectable to and disconnectable from the drive means, wherein the signal transfer is carried out via a connection means when the said memory portion is set in the drive portion. In this information recording and reproducing apparatus, since the recording portion can be freely connected to or disconnected from the drive portion, it is possible to selectively insert portable substrates storing different information in the same apparatus body portion.

Abstract: In a solid state magnetic memory device wherein the information storing region of a Bloch line memory device using Bloch lines generated in magnetic domain walls as information carriers is covered with a magnetic material film having stripe domains perpendicular to the magnetic domain walls, the information storing position is determined by the stripe domains and a memory density of more than several tens giga bits per cm.sup.2 can be realized.

Abstract: The present invention relates to DC-88A and DC-89A1 and their production. These compounds are obtained by fermentation of microorganisms belonging to the genus Streptomyces. These compounds have antibacterial and anti-tumor activities and are useful as medicaments.

Abstract: A pharmacologically acceptable acid addition salt of DC-52 with 0.5-2.0 equivalent weight of inorganic acid, sulfonic acid, acidic amino acid, citric acid, transaconitic acid, .alpha.-ketoglutaric acid, itaconic acid, malonic acid or ascorbic acid on the basis of DC-52, having the same degree of antitumor activity as DC-52, is superior to DC-52 in stability at powdering or at preservation.

Abstract: Phenazine compounds represented by the formula: ##STR1## wherein R is a hydrogen atom, an unsubstituted or substituted lower alkanoyl group, or an unsubstituted or substituted arylcarbonyl group have antibacterial and anti-tumor activities.Some of these compounds are produced by incubation of a microorganism.

Abstract: New substances designated as DC-45-A, DC-45-B.sub.1 and DC-45-B.sub.2 and represented by the following general formula: ##STR1## wherein (i) R.sub.1 and R.sub.2 together with the carbon atom therebetween represent the group ##STR2## and R.sub.3 represents ##STR3## (designated DC-45-A); (ii) R.sub.1 represents --OH, R.sub.2 represents --CH.sub.2 OH and R.sub.3 represents ##STR4## (designated DC-45-B.sub.1); or (iii) R.sub.1 and R.sub.2 together with the carbon atom therebetween represent the group ##STR5## and R.sub.3 represents ##STR6## (designated DC-45-B.sub.2). DC-45-A, DC-45-B.sub.1 and DC-45-B.sub.2 possess antibiotic and anti-tumor activity and may be obtained by culturing a microorganism of the genus Streptomyces. Preferred strain is Streptomyces bottropensis (FERM-P No. 5219; NRRL 12051).