Patents by Inventor Kazumasa Tanida
Kazumasa Tanida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055384Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: ApplicationFiled: October 27, 2023Publication date: February 15, 2024Applicant: ROHM CO., LTD.Inventors: Kazumasa TANIDA, Osamu MIYATA
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Patent number: 11842972Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: GrantFiled: May 24, 2022Date of Patent: December 12, 2023Assignee: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Patent number: 11553118Abstract: An imaging apparatus with reduced flare includes an imaging structure including a solid state imaging element (1) and a transparent substrate (2) disposed on the imaging element. The imaging apparatus includes a circuit substrate (7) including a circuit, a spacer (10) including at least one fixing portion (11) that guides the imaging structure to a desired position on the circuit substrate (7) when the imaging structure is mounted on the circuit substrate, and a light absorbing material (13) disposed on at least one side surface of the imaging structure such that that light absorbing material (13) is between the imaging structure and the at least one fixing portion.Type: GrantFiled: June 22, 2018Date of Patent: January 10, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Katsuji Kimura, Kazumasa Tanida, Fumihiko Hanzawa
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Publication number: 20220285305Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Applicant: ROHM CO., LTD.Inventors: Kazumasa TANIDA, Osamu MIYATA
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Patent number: 11355462Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: GrantFiled: September 30, 2020Date of Patent: June 7, 2022Assignee: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Publication number: 20210013168Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Applicant: ROHM CO., LTD.Inventors: Kazumasa TANIDA, Osamu MIYATA
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Patent number: 10818628Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: GrantFiled: December 4, 2019Date of Patent: October 27, 2020Assignee: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Publication number: 20200145562Abstract: An imaging apparatus with reduced flare includes an imaging structure including a solid state imaging element (1) and a transparent substrate (2) disposed on the imaging element. The imaging apparatus includes a circuit substrate (7) including a circuit, a spacer (10) including at least one fixing portion (11) that guides the imaging structure to a desired position on the circuit substrate (7) when the imaging structure is mounted on the circuit substrate, and a light absorbing material (13) disposed on at least one side surface of the imaging structure such that that light absorbing material (13) is between the imaging structure and the at least one fixing portion.Type: ApplicationFiled: June 22, 2018Publication date: May 7, 2020Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Katsuji KIMURA, Kazumasa TANIDA, Fumihiko HANZAWA
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Publication number: 20200105699Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Applicant: ROHM CO., LTD.Inventors: Kazumasa TANIDA, Osamu MIYATA
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Patent number: 10522494Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: GrantFiled: November 8, 2017Date of Patent: December 31, 2019Assignee: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Patent number: 10090351Abstract: A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.Type: GrantFiled: May 5, 2017Date of Patent: October 2, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroaki Ashidate, Kazumasa Tanida
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Patent number: 9935232Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes a step of grinding to thin a first semiconductor wafer on which a semiconductor device is formed in a state in which a surface of a second semiconductor wafer is fixed on a chuck table of a grinding device after bonding the first semiconductor wafer to the second semiconductor wafer. The method includes a step of fixing a surface of the first semiconductor wafer on the chuck table and grinding the surface of the second semiconductor wafer in a state in which the first semiconductor wafer is bonded to the second semiconductor wafer prior to the grinding step to thin the first semiconductor wafer.Type: GrantFiled: November 4, 2015Date of Patent: April 3, 2018Assignee: Toshiba Memory CorporationInventors: Gen Toyota, Shouta Inoue, Susumu Yamamoto, Takamasa Tanaka, Takamitsu Yoshida, Kazumasa Tanida
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Publication number: 20180068970Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Applicant: ROHM CO., LTD.Inventors: Kazumasa TANIDA, Osamu MIYATA
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Patent number: 9831204Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: GrantFiled: June 28, 2017Date of Patent: November 28, 2017Assignee: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Publication number: 20170301640Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.Type: ApplicationFiled: June 28, 2017Publication date: October 19, 2017Applicant: ROHM CO., LTD.Inventors: Kazumasa TANIDA, Osamu MIYATA
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Patent number: 9761463Abstract: According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.Type: GrantFiled: May 21, 2015Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazumasa Tanida, Takamitsu Yoshida, Kuniaki Utsumi, Atsuko Kawasaki
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Publication number: 20170243910Abstract: A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.Type: ApplicationFiled: May 5, 2017Publication date: August 24, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hiroaki ASHIDATE, Kazumasa TANIDA
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Patent number: 9721865Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.Type: GrantFiled: August 12, 2015Date of Patent: August 1, 2017Assignee: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Patent number: 9679867Abstract: A semiconductor device includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.Type: GrantFiled: October 30, 2015Date of Patent: June 13, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Ashidate, Kazumasa Tanida
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Publication number: 20160268469Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes a step of grinding to thin a first semiconductor wafer on which a semiconductor device is formed in a state in which a surface of a second semiconductor wafer is fixed on a chuck table of a grinding device after bonding the first semiconductor wafer to the second semiconductor wafer. The method includes a step of fixing a surface of the first semiconductor wafer on the chuck table and grinding the surface of the second semiconductor wafer in a state in which the first semiconductor wafer is bonded to the second semiconductor wafer prior to the grinding step to thin the first semiconductor wafer.Type: ApplicationFiled: November 4, 2015Publication date: September 15, 2016Inventors: Gen Toyota, Shouta Inoue, Susumu Yamamoto, Takamasa Tanaka, Takamitsu Yoshida, Kazumasa Tanida